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Drain current vs gate voltage, , experimental characteristics are shown only at 300, 330, and 355 K for the SOI Fe-MOSFET (with equal width and length, ). The loop frequency of the measurement is about 10 mHz. The leakage current floor (defined here as the current for gate voltage smaller than −1 V) exponentially increases by increasing the temperature but the remains always higher than . The analysis suggests that for our ferroelectric gate stack. The inset shows an FIB cross section image with the thickness of the different gate stack layers and the schematic of the capacitive model of the device.
Transconductance, , as a function of the gate voltage, , for the sweeping up branch of the curve (a smoothing has been performed by averaging eight adjacent points) calculated by numerical derivation of the current curve. A very significant improvement is observed from ambient temperature up to (curves at 340 and 355 K), followed by a degradation (curves at 370 and 395 K), which correspond to the gate stack increase and decrease with the temperature.
SS, as a function of T and a minimum is clearly visible at the transition temperature of the ferroelectric material, as predicted by the analytical model. The values of SS are extracted at each temperature by a linear interpolation method in the subthreshold region. The inset shows the detailed, numerically calculated vs plot, at different temperatures; the data clearly confirms that the minimum of each curve decreases till and then degrades for .
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