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(a) Typical I-V characteristics of the bi-layer resistive switching memory devices measured by DC double sweep. set compliance current was enforced and different reset stop voltages (−2.1, −2.7, and −3.3 V) were used to achieve multilevel HRS. (b) Three HRS states obtained by pulse testing using programming scheme 1): fixed pulse width (50 ns) with different pulse amplitudes (−2.3, −2.6, and −2.9 V). (c) Three HRS states obtained by pulse testing using programming scheme 2): fixed pulse amplitude (−2.3 V) but different pulse widths (50 ns, 500 ns, and ).
Measured voltage-time relationship: pulse amplitudes needed to successfully trigger the set/reset switching at the some fixed pulse widths. The success of the trigger is defined to meet predefined target LRS/HRS resistances .
(a) Simulated cell resistance evolution with time after reset pulses are applied. States A, B, C are achieved by varying pulse amplitudes, and their equivalent states , , are achieved by varying pulse widths. (b) Simulated switching time and the energy consumption for achieving target resistance for different reset pulse amplitudes.
Transient response current waveform for the two reset programming schemes. The first scheme: −2.3 V/50 ns; the second scheme: −2 V/500 ns. The initial resistance is , and the final resistance is . Also the current waveform predicted by the model is plotted. The energy consumption for the first scheme (−2.3 V/50 ns) is about 7.4 pJ and for the second scheme (−2 V/500 ns) is about 60.9 pJ.
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