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[(a)–(d)] TEM images of Ge NWs grown from Au colloids at and subject to temperature ramp up to followed by deposition of Ge shells at for 2 min [(e)–(h)], same as in [(a)–(d)], however, with a low temperature Si blocking layer step between core and shell growth. [(i)–(k)] TEM images of Ge/Si core/shell NWs without a low temperature Si barrier layer. [(l)–(n)] TEM images of Ge/Si core/shell NWs grown at with a low temperature Si barrier layer and a input during temperature ramp (10 min) and Si shell deposition (7 min). Inset: (m) is a magnified image near the wire surface. Inset: (l) is an EDX line scan across the diameter of a 16 nm diameter Ge/Si core/shell NW.
(a) Illustration of a Ge/Si core/multishell NW structure used as an input for Silvaco Atlas 3D simulations. (b) simulations: energy band-edge diagram and free hole density radial distribution for i) 6 nm/1 nm/2 nm i-Ge core/-Ge/i-Si with (solid line), and for ii) 7 nm core/2 nm radial p-Ge/i-Si with (dashed line), with similar areal doping densities. (c) Simulated transfer curves for the doping scenarios described in text showing higher on-current, and therefore higher transconductance for core/multishell approach. (d) for the core/multishell approach as function of Ge-shell acceptor doping density .
(a) Oblique-angle SEM image of a Ge/Si core/multishell NW HFET. (b) Measured output curves for two devices without (solid lines) and with (dashed lines) Au diffusion both for the same gate voltage steps and same . (c) Transfer curves of HFET devices with and without Au diffusion on devices with two different channel lengths showing higher on-currents and transconductances for the case of no Au diffusion. (d) Plot of the transconductance as a function of , the slope of which gives the mobility-capacitance product, which is higher for the NWs with no Au diffusion.
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