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(a) Atomic structure of slab model and band gap profile along z-axis; the triangles represent CBE and VBE of each cation along z-axis such as Si in Si and layers and Hf in layers. The CBE and VBE are determined by the criterion of integrated LDOS value change, less than 0.0001. In the slab model, the gold (gray), red (black), blue (dark gray), and white balls represent Si, O, Hf, and H atoms, respectively (in grayscale figure). (b) Spatial variation in planar averaged local static dielectric constants along z axis; in both (a) and (b), the vertical dotted lines represent interfaces between and . (c) and (d) show CBE and dielectric-constant profiles, respectively, resulted from using the linear, abrupt, and ESL models for device-level simulations of the stack with the assumed IL thickness of 5 Å.
(a) Capacitance of a MOS device with gate stack calculated from using different interface models; the capacitance is scaled by the gate oxide capacitance . Inset shows the CBE (solid lines) and the inversion charge densities (dashed lines) calculated from using the AB-AD model (squares) and the LB-LD model (diamonds). The left and right axis represent CBE (electron volt) and electron density , respectively. (b) Drain current (solid lines with symbols) and gate current (dashed lines) of a DG-MOSFET with the stack (nominal EOT of 0.8 nm); the channel is intrinsically doped and the source and drains are n-doped with the doping concentration of . For drain currents, left and right axis is in the log and linear scales, respectively. Top and bottom axes for the log and linear scales, respectively, are scaled differently.
(a) On-current and gate-leakage current evaluated at the drain-current minimum vs the nominal EOT of gate stack. (b) vs using LD and AD models. Bulk value is also shown for reference.
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