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(a) Cross-sectional HR-TEM image of structure after annealing at for 30s in air ambient. (b) Cross-sectional magnified HR-TEM image of layer. (c) EDS spectrum of annealed sample. The inset is the HR-XRD double axis profile of heterostructure.
(a) High frequency (1 MHz) capacitance vs gate voltage (C-V) characteristics of control, as-deposited and annealed devices. Decrease in capacitance for as-deposited and annealed devices is due to the oxide capacitance. C-V characteristics of (b) as-deposited (c) annealed devices with different positive programming pulse. (d) C-V curve of annealed device with varying frequency from 500 KHz to 500 Hz.
(a) Schematic band diagram of MOS structure. (b) Current density (J) vs gate voltage (V) characteristic of annealed device with reverse and forward bias.
Room temperature (a) retention (b) endurance characteristics of the annealed device.
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