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(Left) Layer sequence of the submicron-sized RTD. The double barrier consists of undoped 15 nm thick GaAs buffer layers, 3 nm thick barriers, and a 4 nm GaAs quantum well. (Right) Electron microscopy pictures of a branched RTD with a diameter together with the electronic circuit diagram. The dc working point voltage sets the working point of the RTD in the bistable regime. Additionally a time periodic signal with amplitude as well as an external noise source with standard deviation is applied. On each branch the logic inputs with switching voltages and are applied, and the voltage drop either at or is serving as output.
(a) Current-voltage characteristic of the branched RTD. At the working point a sine-wave periodic signal is applied, so that the bistable system is operated close to the threshold value . (b) Time series of the RTD output current I for the intrinsic noise level operated close to the threshold. Noise-induced neuronlike signal spikes are generated.
(a) Experimentally determined as a function of the noise power for logic inputs , 1, and 2 with switching voltages (0 mV) and (2 mV). The logical output is 1 for values exceeding the threshold voltage of 110 mV, and 0 below. is below the threshold for smaller than 0.7 nW and above for greater than 2 nW. No logic-gate operation can be depicted. Contrary, between and 1.2 nW the logical output is 1 only for both logical inputs 0. This fulfills the truth table of a logic NOR gate. Instead, for noise intensity above 1.2 nW only for both logical inputs 1 the logical output is 0. This can be recognized as a NAND gate. (b) Theoretical simulations with the experimentally obtained parameters agree with the experimental data.
Mean value difference for the NOR and NAND gates as a function of the noise power for the experimental data in (a) and for the theoretically obtained data in (b). The mean value difference is defined as for the logic NOR gate and for the logic NAND gate. Two logic stochastic resonance maxima can be depicted. At the maximum corresponds to the logic NOR and at to the logic NAND gate.
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