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III-V-on-nothing metal-oxide-semiconductor field-effect transistors enabled by top-down nanowire release process: Experiment and simulation
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10.1063/1.3638474
/content/aip/journal/apl/99/11/10.1063/1.3638474
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/11/10.1063/1.3638474
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) (a) Schematic diagram of fin patterning direction, release etching profile, and device alignment to the substrate. (b) Tilted SEM image of fin test structures after fin dry etching and before wire release. (c) Tilted SEM image of fin testing structures after wire release.

Image of FIG. 2.
FIG. 2.

(Color online) (a) Schematic diagram of a III-VON MOSFET with In0.53Ga0.47As channel and Al2O3 gate dielectric from a bird’s eye view. (b) Cross sectional view of a III-VON MOSFET in x-y plane. (c) Cross sectional view of a III-VON MOSFET in x-z plane.

Image of FIG. 3.
FIG. 3.

(Color online) (a) Source current (left) and gate current (right) versus gate voltage for a Lch = 50 nm III-VON MOSFET with WFin of 40 nm. (b) DIBL versus Lch for III-VON MOSFETs from experiment (square) and simulation (hollow square) compared to that of InGaAs FinFET (circle).

Image of FIG. 4.
FIG. 4.

(Color online) (a) DIBL versus Lch for III-VON MOSFETs with different HFin from TCAD simulation. (b) Threshold voltage roll-off property of III-VON MOSFETs with different HFin from TCAD simulation.

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/content/aip/journal/apl/99/11/10.1063/1.3638474
2011-09-15
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: III-V-on-nothing metal-oxide-semiconductor field-effect transistors enabled by top-down nanowire release process: Experiment and simulation
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/11/10.1063/1.3638474
10.1063/1.3638474
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