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(Color online) (a) A 10 ms 150 mA pulse through the write line turns “on” the SV (free MF and pinned MP layer moments are parallel), and a SPB will be trapped as it passes nearby. (b) A 10 ms-100 mA pulse turns “off” the SV (MF and MP are antiparallel), and the SPB is released. The read line and passivation layer are not shown.
(Color online) (a) Cross-sectional schematic of the microfluidic chip. (b) Optical image of the chip containing two addressable write lines (Write1 and Write 2) spaced 2 or 4 μm apart (4 μm shown above). Each write line has one read line to detect the state of one of the twelve 1 μm × 8 μm SV elements on each write line.
(Color online) (a) Write line current and pulse sequence to transport the SPBs down the SV ladder. (b) GMR of a proximal SV on each write line. The SV is ON when the GMR = 0 and OFF when the GMR = ∼3%. The peaks in the GMR, which occur at the switching events, are due to momentary heating due to the write currents. The observed lag between the switching event and the write pulse is due to artifacts (long time constants) in the measurement circuit and is not due to an intrinsic delay in the SV switching process.
(Color online) Video frames and schematics illustrating the transportation of 2.8 μm SPBs between and down the two write lines, in a zig-zag fashion from SV D to F, by use of the pulse sequence shown in Fig. 3. The state of the SVs on each line is labeled as either “on” or “off.”
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