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Vertically integrated silicon-germanium nanowire field-effect transistor
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10.1063/1.3660244
/content/aip/journal/apl/99/19/10.1063/1.3660244
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/19/10.1063/1.3660244
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Figures

Image of FIG. 1.
FIG. 1.

(Color online) (a) Forty-five degree tilted SEM image of a wrap gated Six-Ge1−x nanowire. The gate length is around 200 nm. (b) Forty-five degree tilted SEM picture of the top of an oxidized SiGe nanowire before the top contact realization. We can clearly see the oxide shell whose thickness is around 25 nm. (c) Schematic of the SiGe NW based vertical transistor. (d) Electrical schematic of a vertical device.

Image of FIG. 2.
FIG. 2.

(Color online) (a) Typical output characteristic of a SiGe nanowire based vertical transistor for various gate voltages with VDS varying from −0.5 to 0.5 V. (b) IDS–VGS characteristics at various drain-source voltages. The inset shows the threshold voltage value around 3.9 V. This value remains constant when varying VDS. The highest value of the hysteresis was obtained for VDS = −0.4 V and was measured around 80 mV.

Image of FIG. 3.
FIG. 3.

(Color online) (a) Typical IDS–VGS characteristic of a planar device. The insets show the schematic of a planar device using a SiGe NW as conduction channel and a SEM picture of the device. (c) Typical IDS–VGS characteristic of a vertical device. Both measurements were performed with a drain voltage of −0.2 V.

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/content/aip/journal/apl/99/19/10.1063/1.3660244
2011-11-09
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Vertically integrated silicon-germanium nanowire field-effect transistor
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/19/10.1063/1.3660244
10.1063/1.3660244
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