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(Color online) Gate current (IG ) curves measured in MOSFETs after SET and RESET operations. After SET operation (Igl = 2 μA for SET), RESET has been performed by applying either (a) a negative VG sweep or a (b) FGA treatment (H2 (1%)/N2) at 425 °C for 30 min. (c) IG-VG curves after negative VG sweep and FGA treatment RESET are similar, having the equivalent effect to RESET the device to HRS (Igl = 10 μA for SET).
(Color online) IG-VG current simulated and measured on MOSFET gate stack before and after SET. For fresh devices, a uniform distribution of defects (∼3 · 1019 cm−3) is considered. For simulating IG after SET, the CF properties have been extracted from BD simulations performed using the model in Ref. 15. After SET, a dominant CF with a 2 nm radius is formed inside the HfO2 stack.
(Color online) (a) ID-VG characteristics were measured after SET and RESET operations in MOSFETs. ID-VG curves show an increase of the VT after SET compared to the fresh device. After the FGA RESET, the VT shifts back approaching its pristine value, i.e., Δ = 0.05 V. The Δ is plotted after SET and RESET operations performed by either the negative VG sweep or the FGA treatment in (b) and (c), respectively. The effects on both IG and VT of both negative VG sweep and FGA treatment are similar.
The TEM micrograph shows the gate stack of a MOSFET (W × L = 0.16 × 0.25 μm2) after a SET operation performed with Igl = 10 μA. No metal filament was observed. The DBIE (Ref. 17) was present at the IL. The BD path serving as the actual switching CF of size within 5 nm was located by the DBIE. The inset shows a complete MOSFET.
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