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Investigation on the characteristics of stress-induced hump in amorphous oxide thin film transistors
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View: Figures


Image of FIG. 1.
FIG. 1.

(Color online) (a) Cross sectional view of a-HIZO TFT along channel length/width directions, respectively (left). TEM images of fabricated a-HIZO TFT (right). (b) Transfer characteristic after applying a negative gate bias with/without the light irradiation.

Image of FIG. 2.
FIG. 2.

(Color online) (a) ID-VG characteristic and transconductance curve. The inset shows the intensity spectrum of white LED used in this experiment. (b) Hump current ratio versus on-current (Ihump/Ion ). With respect to channel width, the measured devices have same length size (12 μm). The inset indicates Ihump/Ion with respect to channel length. The measured devices have same width size (50 μm).

Image of FIG. 3.
FIG. 3.

(Color online) Simulated results indicate electric field distribution on the gate dielectric. (a) Channel length direction. The inset is the TEM image of gate insulator along channel length direction. The thickness of gate insulator at the edge is 24 nm thinner than that at the center. (b) Channel width direction. The inset is the simulated electric field distribution under S/D metal. The sharp S/D metal angle enhances the electric field crowding effect.

Image of FIG. 4.
FIG. 4.

(Color online) (a) ID-VG curves with forward and reverse sweepings after applying a negative gate bias and light stress. (b) ID-VG curves with the sequential sweeping from forward and reverse sweeping on the same TFT stressed by the asymmetric negative bias and light.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Investigation on the characteristics of stress-induced hump in amorphous oxide thin film transistors