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Downscaling effects on self-heating related instabilities in p-channel polycrystalline silicon thin film transistors
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10.1063/1.3621874
/content/aip/journal/apl/99/5/10.1063/1.3621874
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/5/10.1063/1.3621874
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Figures

Image of FIG. 1.
FIG. 1.

(Color online) Transfer characteristics measured before and after different BS times in the self-heating regime: (a) reference device (tox = 60 nm, L = 6 μm, and W = 150 μm) with bias-stress conditions: Vg−VT = −12 V, Vds = −12 V and dissipated power density 6.7 × 10−2 mW/μm2; (b) scaled device (tox = 20 nm, L = 2 μm, and W = 50 μm) with bias-stress conditions: Vg−VT = −4 V, Vds = −4 V and dissipated power density 7 × 10−2 mW/μm2.

Image of FIG. 2.
FIG. 2.

(Color online) Threshold voltage shift, ΔVT, (a) and charge variation ΔQ = CoxΔVT, (b) vs the dissipated power density for the reference device (tox = 60 nm, L = 6 μm, and W = 150 μm) (•), the scaled device (tox = 20 nm, L = 2 μm, and W = 50 μm) (▪), and the partially scaled device (tox = 20 nm, L = 2 μm, and W = 150 μm) (♦). Each data point represents the average value among at least 3 different measurements performed at same power density and the error bars are indicative of max and min measured values. A linear fit of the experimental data is also shown.

Image of FIG. 3.
FIG. 3.

(Color online) (a) Cross-sectional view of the simulated reference device (tox = 60 nm, L = 6 μm, and W = 150 μm) structure with indicated the different layers. (b) Temperature distribution calculated by using a 3D simulation for the reference device fabricated on a glass substrate for bias-conditions giving a dissipated power density of 0.067 mW/μm2 (maximum temperature: 560 K). For clarity, the passivation oxide and the gate oxide have been removed from the picture. Also indicated by the dashed line is the cross-sectional plane reported in (a).

Image of FIG. 4.
FIG. 4.

(Color online) Simulated maximum channel temperature, Tmax, as a function of dissipated power density for the reference device (tox = 60 nm, L = 6 μm, and W = 150 μm) (▴), the scaled device (tox = 20 nm, L = 2 μm, and W = 50 μm) (•), and the partially scaled device (tox = 20 nm, L = 2 μm, and W = 150 μm) (▪).

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/content/aip/journal/apl/99/5/10.1063/1.3621874
2011-08-03
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Downscaling effects on self-heating related instabilities in p-channel polycrystalline silicon thin film transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/99/5/10.1063/1.3621874
10.1063/1.3621874
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