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Polycrystalline silicon TFTs are biased from weak to strong inversion (−4 V ≤ VGS ≤ 4 V). (a) Plots of the measured channel conductance activation energy as a function of the gate voltage. (b) Polycrystalline silicon TFTs channel conductance as a function of T1/4.
Plots of the polycrystalline silicon TFTs channel conductance pre-factor gDS0 as a function of T0 1/4.
Distribution of localized states as a function of the position of the Fermi level in the upper part of the bandgap calculated with c = 4.2, and for 0.3 nm ≤ γ−1 ≤ 3 nm (grey area). Dotted plots: calculated exponential distribution following (4) for γ−1 = 3 nm. The linear fit gives a linear regression coefficient R = 0.989, with error bar ΔN0 = 1.4 × 1021 cm−3 eV−1 and ΔE0 = 1.2 meV.
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