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(Color online) (a) Schematic representation of the two different of samples analyzed within this work. (b) L-I curves measured on one of the analyzed laser diodes at the different stages of a stress test. (c) Threshold current increase measured on the same sample during stress time. (d) Degradation of a LED-like sample (expressed as 1/η-1 as in Ref. 10) submitted to constant current stress. Stress conditions for both LDs and LED-like samples are 4 kA/cm2, 75 °C.
(Color online) (a) Simulated bandstructure of the quantum well region of one of the analyzed devices. The filling and reverse voltage levels used for DLTS analysis are reported in the inset. The gray box represents the semiconductor region crossed by the SCR boundary when voltage is varied between −1 V and 2 V. (b) DLTS signal measured on one of the analyzed samples at the different stages of the stress experiment. Stress conditions for both LDs and LED-like samples are 4 kA/cm2, 75 °C.
(Color online) (a) Degradation of one of the analyzed LED-like samples (expressed as 1/η-1 as in Ref. 10) submitted to constant current stress. (b) Increase in DLTS signal measured on the same device during stress time. Solid lines represent square-root fit of the experimental data.
(Color online) Arrhenius plot for the deep level responsible for the degradation of laser diodes. For comparison, we report the Arrhenius plot of deep levels identified by other groups in bulk-GaN (not in devices submitted to stress).
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