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(Color online) Process flow chart of hybrid surface passivation for n+-on-p HgCdTe long wave detector arrays. (a) covering the thin layer of CdTe dielectric film on rinsed HgCdTe epitaxial film; (b) defining the implantation-window patterns with photolithography and exposing HgCdTe surface as implantation-window patterns after selectively etching CdTe film; (c) depositing ZnS film as implantation barrier layers and implanting B+ into implantation-window patterns to form n+-on-p photodiode arrays; (d) low energy hydrogen plasma modification of photodiodes; (e) removing the barrier layer and photoresist and depositing ZnS film to cover the surface of photodetector arrays to form double-layer passivation, then exposing HgCdTe surface as metallization patterns with selective etching ZnS film and depositing the metallization electrode; (f) fabricated three type surface-passivated pixels in one same chip.
(Color online) Measured dynamic resistance (right axis) and dark current (left axis) with different surface passivation techniques.
(Color online) Measured R-V curves and fitted trap-assisted current components for the conventional technique and in-situ CdTe passivation. The data with hybrid surface passivation are not list in the figure for better view of extracted current components. R exp(dotted) is the experimental data of total dynamic resistance, R fit(dotted) is the fitting data of total dynamic resistance, and R tat(triangular) is the dynamic resistance of trap assisted tunneling current.
Extracted characteristic parameters corresponding to trap-assisted current components by using developed simultaneous current extracting approach.
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