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Advanced Si solid phase crystallization for vertical channel in vertical NANDs
1. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, in Digest of Technical Papers Symposium on VLSI Technology (IEEE, 2007), pp. 14–15.
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3. Y. Fukuzumi, R. Katsumura, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Iwata, H. Aochi, and A. Nitayama, in Technical Digest - International Electron Devices Meeting (IEEE, 2007), pp. 449–452.
4. B. Kim, S.-H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J.-Y. Ahn, H. Choi, K. Hwang, Y. Ko, and C.-J. Kang, in Proceedings of the IEEE International Reliability Physics Symposium (IEEE, 2011), pp. 2E–41–2E4–4.
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The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.
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