Index of content:
Volume 2001, Issue 1, January 2001
- APPLIED PHYSICS REVIEWS
89(2001); http://dx.doi.org/10.1063/1.1361065View Description Hide Description
Many materials systems are currently under consideration as potential replacements for as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.
89(2001); http://dx.doi.org/10.1063/1.1368156View Description Hide Description
We present a comprehensive, up-to-date compilation of band parameters for the technologically important III–V zinc blende and wurtzite compound semiconductors:GaAs,GaSb,GaP,GaN,AlAs,AlSb,AlP,AlN,InAs,InSb,InP, and InN, along with their ternary and quaternary alloys. Based on a review of the existing literature, complete and consistent parameter sets are given for all materials. Emphasizing the quantities required for band structure calculations, we tabulate the direct and indirect energy gaps, spin-orbit, and crystal-field splittings, alloy bowing parameters, effective masses for electrons, heavy, light, and split-off holes, Luttinger parameters, interband momentum matrix elements, and deformation potentials, including temperature and alloy-composition dependences where available. Heterostructure band offsets are also given, on an absolute scale that allows any material to be aligned relative to any other.
90(2001); http://dx.doi.org/10.1063/1.1377023View Description Hide Description
Semi-insulating GaAs shows current oscillations if a high dc voltage is applied to a sample. These oscillations are caused by traveling high-electric-field domains that are formed as a result of electric-field-enhanced electron trapping. This article describes the various types of experiments that have been carried out with this system, including recent ones that use the electro-optic Pockels effect in order to measure the local electric fields in the sample in a highly accurate manner. An historical overview of the theoretical developments is given and shows that no satisfying theory is currently available. A list of all the required ingredients for a successful theory is provided and the experimental data are explained in a qualitative manner. Furthermore, the main electron trap in semi-insulating GaAs is the native defect EL2, the main properties of which are described.
Ultrathin (<4 nm) and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits90(2001); http://dx.doi.org/10.1063/1.1385803View Description Hide Description
The outstanding properties of which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuitdevice scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronicdevices will be manufactured with and Si–O–N for the foreseeable future, continued scaling of integrated circuitdevices, essentially the continued adherence to Moore’s law, will necessitate the introduction of an alternate gate dielectric once the gate dielectric thickness approaches ∼1.2 nm. It is hoped that this article will prove useful to members of the siliconmicroelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors [L. Feldman, E. P. Gusev, and E. Garfunkel, in Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, edited by E. Garfunkel, E. P. Gusev, and A. Y. Vul’ (Kluwer, Dordrecht, 1998), p. 1 [Ref. 1]; E. P. Gusev, H. C. Lu, E. Garfunkel, T. Gustafsson, and M. Green, IBM J. Res. Dev. 43, 265 (1999) [Ref. 2]; R. Degraeve, B. Kaczer, and G. Groeseneken, Microelectron. Reliab. 39, 1445 (1999) [Ref. 3].