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1. H. Y. Kang and C. K. Hwangbo, J. Vac. Sci. Technol. B 27, 58 (2009).
2. S. Lee, I. Lee, J. G. Doh, J. U. Lee et al., J. Vac. Sci. Technol. B 31, 021606 (2013).
3. A. M. Hawryluk and L. G. Seppala, J. Vac. Sci. Technol. B 6, 2162 (1988).
4. H. Kinoshita, K. Kuirhara, Y. Ishii, and Y. Torii, J. Vac. Sci. Technol. B 7, 1648 (1989).
5. J. E. Bjorkholm, J. Bokor, L. Eichner, R. R. Freeman et al., J. Vac. Sci. Technol. B 8, 1509 (1990).
6. P. Silverman, Proc. SPIE 4343, 12 (2001).
7. H. Meiling, J. Benschop, U. Dinger, and P. Kurz, Proc. SPIE 4343, 38 (2001).
8. D. Tichenor, A. K. Ray-Chaudhuri, W. C. Replogle, R. H. Stulen et al., Proc. SPIE 4343, 19 (2001).
9.See, for NXE 3300B EUV exposure tool (last accessed November 4, 2013).
10. B. A. M. Hansson and H. Hertz, J. Phys. D: Appl. Phys. 37, 3233 (2004).
11. B. A. M. Hansson, I. V. Fomenkov, N. R. Bowering et al., Proc. SPIE 6151, 61510R (2006).
12. Y. Teramoto, G. Niimi, and D. Yamatani et al., Proc. SPIE 6151, 615147 (2006).
13. J. R. Freeman, S. S. Harilal, and A. Hassanein, J. Appl. Phys. 110, 083303 (2011).
14. R. Peeters, S. Lok, E. van Alphen, N. Harned et al., “ ASML's NXE performance and volume introduction,” Proc. SPIE 8679, 86791F (2013).
15. S. Bajt, J. Alamceda, T. Barbee, Jr., W. M. Clift, J. A. Folta, B. Kaufmann, and E. Spiller, Proc. SPIE 4506, 65 (2001).
16. U. Kleineberg, T. Westerwalbesloh, O. Wehmeyer, M. Sundermann, A. Brechling, U. Heinzmann, M. Haidl, and S. Mullender, Proc. SPIE 4506, 113 (2001).
17. T. Higashiguchi, T. Otsuka, N. Yugami, W. Jiang et al., Appl. Phys. Letts. 99, 191502 (2011).
18. T. Otsuka, D. Kilbane, T. Higashiguchi, N. Yugami et al., Appl. Phys. Letts. 97, 231503 (2010).
19. S. Raghunathan, G. McIntyre, G. Fenger, and O. Wood, Proc. SPIE 8679, 867918 (2013).
20. S. L. Nyabero, R. W. E. van de Kruijs, A. E. Yakshin, and F. Bijkerk, Appl. Phys. Letts. 103, 093105 (2013).
21. J. S. Taylor, G. E. Sommargren, D. W. Sweeney, and R. M. Hudyma, Proc. SPIE 3331, 580 (1998).
22. F. Tardif, O. Raccurt, J. C. Barbe, F. De Crecy et al., Electrochem. Soc. Proc. 26, 153 (2003).
23. M. H. Jung, H. W. Kim, J. Hong, S. G. Woo, H. K. Cho, and W. S. Han, Proc. SPIE 5376, 1100 (2004).
24. D. L. Goldfarb, J. J. de Pablo, P. F. Nealey, J. P. Simons, W. M. Moreau, and M. Angelopoulos, J. Vac. Sci. Technol. B 18, 3313 (2000).
25. H. Namatsu, Proc. SPIE 4688, 888 (2002).
26.ITRS, International Technology Roadmap for Semiconductors 2004 Update, 2004.
27. H. B. Cao and P. F. Nealey, J. Vac. Sci. Technol. B 18, 3303 (2000).
28. A. Jouve, J. Simon, A. Pikon, H. Solak, C. Vannuffel, and J.-H. Tortai, Proc. SPIE 6153, 61531C (2006).
29. J. M. Hutchinson, Proc. SPIE 3331, 531 (1998).
30. H. Cao, W. Yueh, B. Rice, J. Roberts, T. Bacuita, and M. Chandhok, Proc. SPIE 5376, 757 (2005).
31. J. A. Folta, J. C. Davidson, C. C. Larson, C. C. Walton, and P. A. Kearney, Proc. SPIE 4688, 173 (2002).
32. A. Wagner, M. Burkhardt, A. B. Clay, and J. P. Levin, J. Vac. Sci. Technol. B 30, 051605 (2012).
33. H. Zhang, Y. Du, M. D. F. Wong, Y. Deng, and P. Mangat, “ Layout small-angle rotation and shift for EUV defect mitigation,” in IEEE ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, 5–8 November 2012, pp. 4349.
34. A. A. Kagalwalla and P. Gupta, IEEE Trans. Semicond. Manuf. 26, 111 (2013).
35. S. Jeong, Y. Lin, L. Johnson, S. Rekawa, M. Jones, P. Denham, P. Batson, R. Levesque, P. Kearney, P.-Y. Yan, E. Gullikson, J. H. Underwood, and J. Bokor, J. Vac. Sci. Technol. B 16, 3430 (1998).
36. S. Jeong, L. Johnson, S. Rekawa, C. C. Walton, S. T. Prisbrey, E. Tejnil, J. H. Underwood, and J. Bokor, J. Vac. Sci. Technol. B 17, 30093013 (1999).
37. E. Tejnil and A. Stivers, Proc. SPIE 3873, 792 (1999).
38. T. Haga, H. Takenaka, and M. Fukuda, J. Vac. Sci. Technol. B 18, 2916 (2000).
39. L. E. Klebanoff and D. J. Rader, U.S. patent 6,153,044 (2000).
40. L. E. Klebanoff and D. J. Rader, U.S. patent 6,253,464 (2001).
41. D. J. Rader, D. E. Dedrick, E. W. Beyer, A. H. Leung, and L. E. Klenbanoff, Proc. SPIE 4688, 182 (2002).
42. D. E. Dedrick, E. W. Beyer, D. J. Rader, L. E. Klebanoff, and A. H. Leung, J. Vac. Sci. Technol. B 23, 307 (2005).
43. Y. A. Shroff, M. Leeson, and P. Y. Yan, J. Vac. Sci. Technol. B 28, C6E36 (2010).
44. H. Y. Kang, P. Peranantham, C. K. Hwangbo, H. S. Seo, S. S. Kim, and J. H. Lee, J. Vac. Sci. Technol. B 30, 06F505 (2012).
45. Y. R. Park, J. H. Ahn, J. S. Kim, B. S. Kwon et al., J. Vac. Sci. Technol. A 28, 761 (2010).
46. Y. Guillou and A. M. Dutron, “ 3D IC products using TSV for mobile phone application: An industrial perspective,” in European Microelectronics Packaging Conference, IMAPS, Rimini, Italy, 15–18 June 2009, pp. 16.
47. G. S. Sandhu, “ 3D integration landscape–—Opportunities and hazards,” in 3-D Architectures for Semiconductor Integration and Packaging Conference, Technology Venture, Burlingame, California, USA, 17–19 November 2008, pp. 16.
48. G. Humpston, “ Novel and low cost through silicon via solution for wafer scale packaging of image sensors,” in IEEE Electrical Design of Advanced Packaging and Systems Symposium, Seoul, Korea, 10–12 December 2008, pp.179182.
49.International Technology Roadmap for Semiconductor (ITRS)—Executive Summary, 2011, p. 2.
50. K. P. Stuby, U.S. patent 3,648,131 (7 March 1972).
51. S. Linder, H. Baltes, F. Gnaedinger, and E. Doering, “ Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers,” in IEEE Proceeding of MEMS, Oiso, Japan, 25–28 January (1994), pp. 349354.
52. P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland et al., “ Through silicon via technology—Processes and reliability for wafer-level 3D system integration,” in IEEE Electronic Components and Technology Conference, Lake Buena Vista, Florida, USA, 27–30 May 2008, pp. 841846.
53. P. Ramm, A. Klumpp, J. Weber, N. Lietaer et al., “ 3D integration technology: Status and application development,” in Proceedings of the IEEE ESSCIRC, Seville, Spain, 14–16 September 2010, pp. 916.
54.See for hybrid memory cube (last accessed January 24, 2014).
55. L. McIlrath, W. Ahmed, and A. Yip, “ Design tools for the 3D roadmap,” in IEEE International Conference on 3D System Integration, San Francisco, California, USA, 28–30 September 2009, pp. 14.
56. P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer et al., “ 3D monolithic integration,” in IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 15–18 May 2011, pp. 22332236.
57. S. Wong, A. El-Gamal, P. Griffin, Y. Nishi et al., “ Monolithic 3D integrated circuits,” in IEEE International Symposium on VLSI Technology, Systems and Applications, Hsinchu, Taiwan, 23–25 April 2007, pp. 14.
58. R. Ishihara, N. Golshani, J. Derakhshandeh, R. R. Tajari Mofrad, and C. I. M. Beenakker, “ Monolithic 3D-ICs with single grain silicon thin film transistor,” in 12th IEEE International Conference on Ultimate Integration on Silicon (ULIS), Cork, Ireland, 14–16 March 2011, pp. 14.
59. Y. T. Liu, M. H. Lee, H. T. Chen, C. F. Huang et al., “ Thermal accumulation improvement for fabrication manufacturing of monolithic 3D integrated circuits,” in 9th IEEE International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, 20–23 October 2008, pp. 12071210.
60. D. C. Sekar and Z. Or-Bach, “ Monolithic 3D-IC with single crystal silicon layers,” in IEEE International 3D System Integration Conference, Osaka, Japan, 30 January–2 February 2012, pp. 12.
61. C. Ryu, J. Park, J. S. Pak, K. Lee et al., “ Suppression of power/ground inductive impedance and simultaneous switch noise using silicon through-via in a 3-D stacked chip package,” Microwave Wireless Compon. Lett. 17, 855 (2007).
62. M. Hogan, “ Robust verification of 3D-ICs: Pros, Cons and recommendations,” in IEEE International Conference on 3D System Integration, San Francisco, 28–30 September 2009, pp. 16.
63. J. Cong, J. Wei, and Y. Zhang, “ A thermal-driven floorplanning algorithm for 3D ICs,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, 7–11 November 2004, pp. 306313.
64. J. Cong, G. Luo, J. Wei, and Y. Zhang, “ Thermal-aware 3D IC placement via transformation,” in Proceedings of the IEEE 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, 23–26 January 2007, pp. 780785.
65. A. Dimoulas et al., Advanced Gate Stacks for High-Mobility Semiconductors (Springer, Berlin, Heidelberg, New York, 2007), pp. 119.
66. T. Shinichi et al., Carrier-Transport-Enhanced CMOS Using New Channel Materials and Structures (ISDRS, College Park, 2007), pp. 12.
67. Y. Fkih, P. Vivet, B. Rouzeyre, M. L. Flottes et al., “ A 3D IC BIST for pre-bond test of TSVs using ring oscillators,” in 11th IEEE International New Circuits and Systems Conference, Paris, France, 16–19 June 2013, pp. 14.
68. B. Chakraborty and M. Dalui, “ A segmented CA based approach to test TSVs in 3D IC,” in 4th IEEE International Conference on Intelligent Systems, Modeling and Simulation, Bangkok, Thailand, 29–31 January 2013, pp. 669673.
69. P. Y. Chen et al., “ On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding,” in 28th IEEE VLSI Test Symposium, Santa Cruz, California, 19–22 April 2010, pp. 263268.
70. M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, IEEE Trans. Compon., Packag. Manuf. Technol. 1, 1718 (2011).
71. C. Wang, J. Zhou, B. Zhao, X. Liu et al., “ Self-test methodology and structures for pre-bond TSV testing in 3D-IC system,” in IEEE Asian Solid-State Circuits Conference, Kobe, Japan, 12–14 November 2012, pp. 393396.
72. C. O'Sullivan, P. M. Levine, and S. Garg, “ Vertically addressed test structures (VATS) for 3D IC variability and stress measurements,” in 14th IEEE International Symposium on Quality Electronic Design, Santa Clara International Symposium on Quality Electronic Design, Santa Clara, California, 4–6 March 2013, pp. 96–103.
73. S. Mohanram, D. Brenner, and D. Kudithipudi, “ Hierarchical optimization of TSV placement with Inter-tier liquid cooling in 3D-IC MPSoCs,” in 29th IEEE Semiconductor Thermal Measurement & Management Symposium, San Jose, California, 17–21 March 2013, pp. 712.
74. A. Heinig and C. Sohrmann, “ Multi-step approach for thermal optimization of 3D-IC and package,” in IEEE International 3D Systems Integration Conference, Osaka, Japan, 31 January–2 February 2012, pp. 15.
75. H. H. Yeh, S. H. Huang, and K. H. Li, “ 3D IC design partitioning for temperature rise minimization,” in 6th IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference, Taipei, Taiwan, 19–21 October 2011, pp. 447450.
76. A. Gevorgyan, “ 3D IC cooling mechanism by using signaling vias,” in 13th IEEE International Scientific Conference Electronics and Nanotechnology, Kiev, Ukraine, 16–19 April 2013, pp. 140143.
77. P. Y. Hsu, H. T. Chen, and T. T. Hwang, “ Stacking signal TSV for thermal dissipation in global routing for 3D IC,” in 18th IEEE Asia and South Pacific Design Automation Conference, Yokohama, Japan, 22–25 January 2013, pp. 699704.
78. Y. Chen, E. Kursun, D. Motschman, C. Johnson, and Y. Xie, “ Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs,” in IEEE International Symposium on Low Power Electronics and Design, Fukuoka, Japan, 1–3 August 2011, pp. 397402.
79. A. Yu, N. Khan, G. Archit, D. Pinjala et al., “ Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package,” in IEEE Electronic Components and Technology Conference, Lake Buena Vista, Florida, USA, 27–30 May 2008, pp. 2428.
80. T. G. Yue, T. S. Pin, N. Khan, D. Pinjala et al., “ Fluidic interconnects in integrated liquid cooling systems for 3-D stacked TSV modules,” in 10th IEEE Electronics Packaging Technology Conference, Singapore, 2–12 December 2008, pp. 552558.
81. Y. Zhang and M. S. Bakir, Electron. Lett. 49, 404 (2013).
82. Y. Zhang, C. R. King, Jr., J. Zaveri, Y. J. Kim et al., “ Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology,” in IEEE Electronic Components and Technology Conference, Lake Buena Vista, Florida, May 31–June 2011, pp. 20372044.
83. B. Shi, A. Srivastava, and A. Bar-Cohen, “ Hybrid 3D-IC cooling system using micro-fluidic cooling and thermal TSVs,” in IEEE Computer Society Annual Symposium on VLSI, Amherst, Massachusetts, 19–21 August 2012, pp. 3338.
84. N. Khan, V. S. Rao, S. Lim, H. S. We et al., “ Development of 3D silicon module with TSV for system in packaging,” in IEEE Electronic Components and Technology Conference, 2008, pp. 550555.
85. K. Athikulwongse, A. Chakraborty, J. S. Yang, D. Z. Pan, and S. K. Lim, “ Stress-driven 3D-IC placement with TSV keep-out zone and regularity study,” in IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 7–11 November 2010, pp. 669674.
86. C. S. Smith, “ Piezoresistance effect in germanium and silicon,” Phys. Rev. 94, 42 (1954).
87. C. Okoro, M. Gonzalez, B. Vandevelde, B. Swinnen et al., “ Prediction of the influence of induced stresses in silicon on CMOS performance in a Cu–through-via interconnect technology,” in IEEE International Conference on Digital Object Identifier, London, UK, 16–18 April 2007, pp. 17.
88. Q. Zou, T. Zhang, E. Kursun, and Y. Xie, “ Thermomechanical stress-aware management for 3D IC designs,” in IEEE Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, 18–22 March 2013, pp. 12551258.
89. J. S. Pak, J. Kim, J. Lee, H. Lee et al., “ Sharing power distribution networks for enhanced power integrity by using through-silicon-via,” in IEEE Electrical Design of Advanced packaging and Systems Symposium, Seoul, Korea, 10–12 December 2008, pp. 912.
90. K. Mazumdar and M. Stan, “ Breaking the 3D IC power delivery wall,” in IEEE Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, 4–7 November 2012, pp. 741746.
91. D. H. Kim, S. Kim, and S. K. Lim, “ Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs,” in 13th IEEE International Workshop on System Level Interconnect Prediction, 5 June 2011, pp. 18.
92. J. Xie, D. Chung, M. Swaminathan, M. Mcallister et al., “ Electrical-thermal co-analysis for power delivery networks in 3D system integration,” in IEEE International Conference on 3D System Integration, San Francisco, California, USA, 28–30 December 2009, pp. 12.
93. M. Groger, S. M. Harb, D. Morris, W. R. Eisenstadt et al., “ High speed I/O and thermal effect characterization of 3D stacked ICs,” in IEEE International Conference on 3D System Integration, San Francisco, California, USA, 28–30 December 2009, pp. 15.
94. J. Tanskanen, J. Toikka, and E. O. Ristolainen, “ Crosstalk of winning in very small 3D module,” in 36th International Symposium of Microelectronics, IMAPS, Boston, Massachusetts, USA, 18–20 November 2003, pp. 251255.
95. X. Wu, W. Zhao, C. Nimmagadda, M. Nakamoto et al., “ Electrical characterization for intertier connections and timing analysis for 3-D ICs,” IEEE Trans. Very Large Scale Integr. Syst. 20, 186 (2012).
96. I. Savidis and E. G. Friedman, “ Closed-form expressions of 3-D via resistance, inductance and capacitance,” IEEE Trans. Electron Devices 56, 1873 (2009).
97. G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “ Electrical modeling and characterization of through silicon via for three-dimensional ICs,” IEEE Trans. Electron Devices 57, 256 (2010).
98. S. R. Lee and R. Hon, “ Multi-stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration,” in Enabling Technologies for 3-D Integration, edited by C. A. Bower, P. Garrou, P. Ramm, and K. Takahashi (Mater. Res. Soc. Symp. Proc., 2007), Vol. 970, p. 0970Y05.
99. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchoukov, G. Craciun, and P. M. Sarro, J. Micromech. Microeng. 12, 395 (2002).
100. P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, “ Damascene copper electroplating for chip interconnections,” IBM J. Res. Dev. 42, 567 (1998).
101. T. P. Moffat and D. Josell, “ Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns,” J. Electrochem. Soc. 159, D208 (2012).
102. B. Wu and A. Kumar, 3D IC Stacking Technology (McGraw-Hill, New York, USA, 2011), pp. 353404.
103. B. Kim, T. Matthias, M. Wimplinger, and P. Lindner, “ Advanced wafer bonding solutions for TSV integration with thin wafers,” in IEEE International Conference on 3D System Integration, San Francisco, California, USA, 28–30 September 2009, pp. 16.
104. T. Sakai, N. Imaizumi, and T. Miyajima, “ Low temperature Cu–Cu direct bonding for 3D-IC by using fine crystal layer,” in 2nd IEEE CPMT Symposium Japan, Kyoto, Japan, 10–12 December 2012, pp. 14.
105. V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, Clock rate versus IPC: The end of the road for conventional microarchitectures,” in Proceedings of the IEEE 27th Annual International Symposium on Computer Architecture, Vancouver, British Columbia, Canada, 14 June 2000, pp. 248259.
106.“3DIC & TSV Report—Cost, Technologies & Market,” Yole Development, Lyon, France, November 2007.
107. P. G. Emma and E. Kursun, “ Is 3D chip technology the next growth engine for performance improvement?,” IBM J. Res. Dev. 52, 541 (2008).

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Extreme ultraviolet lithography (EUVL) and three dimensional integrated circuit (3D IC) were thoroughly reviewed. Since proposed in 1988, EUVL obtained intensive studies globally and, after 2000, became the most promising next generation lithography method even though challenges were present in almost all aspects of EUVL technology. Commercial step-and-scan tools for preproduction are installed now with full field capability; however, EUV source power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 200 W in-band power at IF, current tools can supply only approximately 40–55 W. EUVL resist has improved significantly in the last few years, with 13 nm line/space half-pitch resolution being produced with approximately 3–4 nm line width roughness (LWR), but LWR needs 2× improvement. Creating a defect-free EUVL mask is currently an obstacle. Actual adoption of EUVL for 22 nm and beyond technology nodes will depend on the extension of current optical lithography (193 nm immersion lithography, combined with multiple patterning techniques), as well as other methods such as 3D IC. Lithography has been the enabler for IC performance improvement by increasing device density, clock rate, and transistor rate. However, after the turn of the century, IC scaling resulted in short-channel effect, which decreases power efficiency dramatically, so clock frequency almost stopped increasing. Although further IC scaling by lithography reduces gate delay, interconnect delay and memory wall are dominant in determining the IC performance. 3D IC technology is a critical technology today because it offers a reasonable route to further improve IC performance. It increases device density, reduces the interconnect delay, and breaks memory wall with the application of 3D stacking using through silicon via. 3D IC also makes one chip package have more functional diversification than those enhanced only by shrinking the size of the features. The main advantages of 3D IC are the smaller form factor, low energy consumption, high speed, and functional diversification. EUVL, if adopted, will continue to enable IC performance improvement at a slower rate, but 3D IC provides an alternative way to improve the system performance. The best scenario is the adoption of both EUVL and 3D IC. However, the possible further delay of EUVL could enhance the realization of 3D IC for IC system improvement.


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