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Chaogates: Morphing logic gates that exploit dynamical patterns
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10.1063/1.3489889
/content/aip/journal/chaos/20/3/10.1063/1.3489889
http://aip.metastore.ingenta.com/content/aip/journal/chaos/20/3/10.1063/1.3489889

Figures

Image of FIG. 1.
FIG. 1.

Template showing different logic patterns for the range of (0–0.5) vs iteration number . Here for and for . is fixed at 0.25 (Ref. 12).

Image of FIG. 2.
FIG. 2.

Simplified schematic of the proof of concept VLSI implementation of an ALU which can switch between at least two arithmetic functions and a completely different function such as a small first-in, first-out memory buffer.

Image of FIG. 3.
FIG. 3.

(Left) Schematic of a two-input, one output morphable chaogate. The gate logic functionality (NOR, NAND, and XOR) is controlled (morphed) in the current VLSI design by global thresholds connected to VT1, VT2, and VT3 through analog multiplexing circuitry and (right) a size comparison between the current chaogate circuitry implemented in the ChaoLogix VLSI chaotic computing chip and a typical NAND gate circuit (courtesy of ChaoLogix, Inc.).

Tables

Generic image for table
Table I.

Truth table of the basic logic operations for a pair of inputs: (Ref. 19). The one-input NOT gate is given by NOT(0) is 1; NOT(1) is 0.

Generic image for table
Table II.

Necessary and sufficient conditions, derived from the logic truth tables, to be satisfied simultaneously by the nonlinear dynamical element, in order for it to have the capacity to implement the logical operations AND, OR, XOR, NAND, NOR, and NOT (cf. Table I) with the same chaogate.

Generic image for table
Table III.

One specific set of solutions of the conditions in Table II which yield the logical operations AND, OR, XOR, and NAND with . Note that these theoretical solutions have been fully verified in a discrete electrical circuit implementing a logistic map (Ref. 4).

Generic image for table
Table IV.

Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the logical operations NAND, AND, NOR, XOR, and OR at different iterations.

Generic image for table
Table V.

Updated state of chaotic logistic map satisfying the conditions in Table IV in order to implement the logical operations NAND, AND, NOR, XOR, and OR during different iterations with , , and .

Generic image for table
Table VI.

Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the logical operations AND, OR, XOR, NAND, and NOR consistently on all possible input sets. Considering in the logistic map function, iteration , threshold level , and , solutions of satisfying the above conditions simultaneously are 0.1, 0.3, 0.35, 0.4, and 0.6, respectively, for AND, OR, XOR, NAND, and NOR logic operations.

Generic image for table
Table VII.

Necessary and sufficient conditions to be satisfied by a nonlinear system in order to implement the logical operations AND, XOR, OR, NAND, XNOR, and NOR, with being the number of evolution steps. For example, when , , and , , 0.05, 0.75, 0.3, 0.425, and 0.5 yield AND, XOR, OR, NAND, XNOR, and NOR logic operations, respectively.

Generic image for table
Table VIII.

Truth table of the half-adder and the necessary and sufficient conditions that implement the half-adder.

Generic image for table
Table IX.

Truth table of half-subtractor and the necessary and sufficient conditions that implement the half-subtractor.

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/content/aip/journal/chaos/20/3/10.1063/1.3489889
2010-09-28
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Chaogates: Morphing logic gates that exploit dynamical patterns
http://aip.metastore.ingenta.com/content/aip/journal/chaos/20/3/10.1063/1.3489889
10.1063/1.3489889
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