Schematics of (a) etched-mesa VCSEL and (b) VCSEL array.
Etched-mesa VCSEL and VCSEL array: schematics of electrical current flow (a) and of heat flow (b). is the thickness of the bottom DBR and is the effective radius of the device’s active region; arrows show the lines of current and heat flow, respectively.
Correction factor for the spreading resistance of a DBR on a perfectly conducting substrate vs relative DBR thickness . Solid line: Obtained from Eq. (3) with ; filled circles: Calculated in Ref. 21 with at , (see Ref. 21 for parameters , , and ).
Thermal resistance vs array size parameter : measured (squares), calculated from Eq. (3) (solid line), and calculated from an homogeneous semi-infinite substrate model (dashed line). Parameters are , , and .
curves (left axis) and temperature rise (right axis) of VCSEL arrays of different sizes: measured (symbols) and calculated (curves).
Active region, top and bottom DBR voltage drops in and arrays in the presence of self-heating (w.SH), as well as bottom DBR voltage drop calculated without the self-heating impact (w.o.SH).
Slope of curves vs array size parameter : measured at temperature rise of (black squares) and (open squares); calculated from Eq. (11) with (solid line) and (dash line).
Parameters of the model of VCSEL arrays emitting at wavelength.
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