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Organic field-effect inversion-mode transistors and single-component complementary inverters on charged electrets
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10.1063/1.2388730
/content/aip/journal/jap/100/11/10.1063/1.2388730
http://aip.metastore.ingenta.com/content/aip/journal/jap/100/11/10.1063/1.2388730
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color) Schematic of the point-to-grid corona triode apparatus with one metallic control wire grid and mask for uniform and large-area deposition and patterning of charge in thin-film electrets. Red curves represent the distribution of electrostatic field lines in air. The green curve represents the breakdown line in air. Magenta circled minus represents the negative ion delivering an electron in air, and magenta circle represents the neutralized molecule which has released the electron. Minus and circled minus represent the electrons and trapped charges, respectively. The charge distribution inside the silicon dioxide is controlled by both the charging and subsequent annealing conditions. is the corona voltage, and is the control grid voltage.

Image of FIG. 2.
FIG. 2.

(Color) (a) Schematic cross section of the organic single-component complementary inverter with an channel enhancement-mode transistor driver on the normal dielectric (with HMDS coating) and a unipolar channel inversion-mode transistor load on a charged region of the dielectric, acting as a space-charge electret. Circled minus represents the volume charges inside negatively charged and annealed oxides. and are the mean charge depth from the free oxide surface (before OSC deposition) and the oxide thickness of a one-side metallized ( as the lower electrode) negatively charged and annealed , respectively. Blue and red plus represents the induced positive charges accumulated at the semiconductor-electret interface and the compensation positive charges on the lower electrode under unbiased conditions. (b) Effective surface potential profile mapping of patterned negatively charged and annealed without optimization of spatial resolution. The effective surface potential significantly increased in charged area “1” with uniform stored-charge distribution, compared to noncharged area “0.”

Image of FIG. 3.
FIG. 3.

(Color online) Drain current vs drain-source voltage output characteristics measured at room temperature for (a) an OFET with normal (HMDS-coated) gate dielectric in accumulation mode ( type) and (b) an OFET with charged electret gate in inversion mode ( type), for utilization in the complementary inverter. is gate voltage. (c) Saturation drain current vs gate voltage transfer characteristics at room temperature of an OFET with (HMDS-coated) gate dielectric in accumulation mode ( for type, right) and an OFET with gate charged electret in inversion mode ( for type, left), for utilization in the complementary inverter.

Image of FIG. 4.
FIG. 4.

(Color online) Water droplets on the surfaces of (a) noncharged (HMDS coated) and (b) charged (HMDS coated) with the effective surface potential of . (c) Contact angle data measured on the surfaces of noncharged and charged (HMDS coated) with different effective surface potential . De-ionized water was used.

Image of FIG. 5.
FIG. 5.

(Color online) (a) Schematic of the setup for the measurement of the charge centroid depth and stored-charge density of negatively corona charged TMS-, by a combination of surface-potential and capacitance-voltage curve measurements using the Si substrate as the semiconductor. Left: Monroe noncontacting probe for the effective surface measurement of free oxide top surface of negatively charged and annealed HMDS-covered samples on -type Si substrate. (Before corona charging, the oxide layer from the rear side of the wafers was removed and an aluminum electrode was evaporated which served as an Ohmic contact to the substrate.) Right: Subsequent measurement of top gate metal-electret-semiconductor (MES) capacitor, with free oxide top surface containing an evaporated gold layer as top gate electrode.). (b) Mean charge depth from the free oxide surface of negatively corona charged oxide samples (with a corona voltage of and a controllable grid voltage of at room temperature) on -type Si substrate after subsequent annealing for at each of the temperatures 25, 80, 100, 150, 200, and , respectively.

Image of FIG. 6.
FIG. 6.

(Color) (a) Left: Monroe noncontacting probe for the top surface potential measurement of negatively charged and annealed TMS- on substrate. Right: Schematic of the setup for the curve measurement of bottom gate organic MES capacitors (The OSC layer was evaporated onto the top of the gate electret, and subsequently a gold layer was deposited on the OSC as metal contact.). (b) Capacitance-voltage curves and threshold voltage shifts (along the arrow direction) of MES capacitors with OSC on negatively charged and annealed with different surface potentials: (label 1), (label 2), (label 3), (label 8), (label 9), (label 10), and (label 11), respectively.

Image of FIG. 7.
FIG. 7.

(Color) Threshold voltage tuning and gradual -to- inversion process control from complete drain current vs gate voltage transfer characteristics for both positive and negative drain-source and gate voltages in the (a) first or the (b) third quadrant at room temperature for OFETs with (HMDS-coated) gate dielectrics possessing the corresponding effective surface potential (which is controlled by the charging and subsequent conditions): (label 1), (label 2), (label 3), (label 4), (label 5), (label 6), (label 7), (label 8), (label 9), (label 10), and (label 11), respectively. for the first quadrant, and for the third quadrant. (c) Effective surface potential dependence of threshold voltage shifts (blue dots: , left) from the first quadrant in Fig. 7(a) and of threshold voltage (red dots: , right) from the third quadrant in Fig. 7(b), respectively. Arrows schematically indicate the threshold voltage shift and gradual -to- inversion process control by the effective potential.

Image of FIG. 8.
FIG. 8.

(Color online) Quasistatic voltage transfer characteristics (solid line) and the corresponding measured gain (dashed line) of the complementary inverter circuits comprised of two transistors on the same chip made from a patterned layer as schematically shown in Fig. 1. The channel dimensions for both OFETs were identical and equal to , and operation frequency . Depending on the polarity of the supply voltage and the electrical connections of source and drain electrodes, the inverters work in the first (a) or the third (b) quadrant. Schematic representations of the corresponding inverter circuit configuration and electrical connections in the two inverters are given in the insets. is input voltage, and is output voltage.

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/content/aip/journal/jap/100/11/10.1063/1.2388730
2006-12-11
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Organic field-effect inversion-mode transistors and single-component complementary inverters on charged electrets
http://aip.metastore.ingenta.com/content/aip/journal/jap/100/11/10.1063/1.2388730
10.1063/1.2388730
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