(Color online) (a) The contact resistance extracted from the same source data using the techniques in the literature. The source data were taken from a set of devices with gold contacts, a thick F8T2 layer, and a PS dielectric. The channel width was and the channel length varied from . GH shows the result of the equivalent circuit model of Horowitz et al. (Ref. 21), AS demonstrates the length scaling of Street and Salleo (Ref. 9), TLM shows the transmission line method (Ref. 22), HS shows the length scaling of Sirringhaus et al. (Ref. 29), curFPP uses the method outlined in this paper with voltage probes dividing the channel into thirds, linFPP (M) uses the standard linear four-point-probe method with the voltage probes dividing the channel into thirds (Ref. 23), and linFPP (E) uses the linear four-point-probe method with the voltage probes close to the electrode to minimize extrapolation error. (b) The source resistance extracted for a wide range of device biases using the method outlined in this paper. Note how the source resistance can be extracted even far into the saturation regime.
(Color online) (a) The best fit to the contact resistance of a gold contact with a thick F8T2 layer, assuming current crowding with a constant contact resistivity. The experimental data are shown as circles and the fit as a solid line. The inset shows a schematic diagram illustrating the current crowding. (b) If the source contact resistivity is extracted on a point-by-point basis, the resulting resistivities fit the functional form . Data for different thicknesses of the semiconducting film are shown. Films thinner than the electrode thickness display anomalously high resistivities due to incomplete step coverage at the contact edge. The data from the thick device have been halved for clarity.
(Color online) A plot of charge density vs perpendicular distance from the dielectric interface for a semiconductor with an exponential density of states with a disorder parameter of . The figure was calculated by the method in Ref. 32 and simulates a device with a dielectric capacitance of and the applied gate bias being increased from .
(a) Current voltage curve of a contact on a thick F8T2 device. When the contact voltage is negatively biased, the contact is acting as the source, and when positively biased, it is the drain. The gate voltage was varied between and in steps. (b) The same measurements taken on a device with a thick F8T2 layer.
(Color online) (a) Simulated three dimensional potential profile of a device with a thick semiconducting layer. The electrodes are shown as yellow rectangles. The dielectric layer in the simulations was thick and the applied gate bias was . The semiconductor model was a pentacene model with an exponential tail of band states with a disorder parameter of . Only the potential in the semiconducting layer is shown. The approximate contact potential drops are indicated by the arrows. (b) The simulated profile of a device with an thick semiconducting layer.
Article metrics loading...
Full text loading...