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Copper ion drift in integrated circuits: Effect of boundary conditions on reliability and breakdown of low- dielectrics
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View: Figures


Image of FIG. 1.
FIG. 1.

Copper interconnects with anode (+ ve voltage) and cathode (grounded).

Image of FIG. 2.
FIG. 2.

Concentration profiles for and cases, , , , , , , and . shoots above eight for at and only a part of this rise (up to 1.4) is shown in the figure.

Image of FIG. 3.
FIG. 3.

(a) Electric field intensity for up to . At , rises up to at and a part of the rise (up to ) has been shown. , , , , , , and . (b) Electric field intensity for up to . , , , , , , and . There is little or no change after in the plotted data.

Image of FIG. 4.
FIG. 4.

profiles for BC. The profiles are similar to the profiles for in Fig. 2. , , , , , , and . The depth of penetration increases with time.

Image of FIG. 5.
FIG. 5.

(a) Time for to reach for various ( range) for the BC. , , , , , , and . As can be seen there is a variation in time to reach with especially at lower . In contrast the time taken for copper ions to reach is almost constant under these conditions. The lower could correspond to a situation with a barrier. (b) Dimensionless time vs Q. The shape of the plot remains the same as in Fig. 5(a).

Image of FIG. 6.
FIG. 6.

Comparison between our simulated TTF vs applied field based on Eqs. (14) and (15) and the experimental median TTF data of Hwang et al. Ref. 20 at for thermal based copper/oxide/silicon (MOS) devices. The error bars in the experimental data indicate the spread in the TTF.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Copper ion drift in integrated circuits: Effect of boundary conditions on reliability and breakdown of low-k dielectrics