SEM image of a typical fabricated recess structured silicon channel with PECVD deposited silicon dioxide.
Schematic diagrams for the possible location of (a) single-dot in device A ( oxidation) and (b) multiple-dot (dotted oval regions) in device B ( oxidation). (c) Simplified equivalent circuit of device B. (d) Schematic illustration of the evolution of individual recess into a single tunnel junction in device A and a single dot in device B.
Measured drain current versus drain voltage for the various voltages of and with at . Decrease in the device resistance due to the increase in the recess gates potential demonstrates the resistance controllability of the device.
Coulomb oscillation characteristics of device A for the gate G4 at . Gates G1 and G3 were grounded.
Contour plot of the drain current as a function of and at of device A with and .
Measured Coulomb oscillation characteristics of device B for the gate G4 at . Gates G1 and G3 were grounded.
(a) Measured drain current contour plot as a function of and at of device B. and . (b) Drain current versus for various values at of device B along the dotted line shown in the Fig. 7(a), and . Shift in the conductance peaks with is marked by the dotted line for the first peak splitting. Data were plotted with drain current offset for the different voltages for clarity.
Temperature depends of the drain current as a function of at , , and of device B [along the dotted line shown in the Fig. 7(a)] for and during thermal cycle 3. Conductance characteristic (shown by dotted lines) is not affected by the different drain voltages or temperatures.
Monte Carlo simulation drain current contour plot as a function and at , , and using the equivalent circuits shown in Fig. 2(c) with outer tunnel junction capacitances of and inner tunnel junction capacitances of .
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