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Voltage-limitation-free analytical single-electron transistor model incorporating the effects of spin-degenerate discrete energy states
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10.1063/1.2838491
/content/aip/journal/jap/103/5/10.1063/1.2838491
http://aip.metastore.ingenta.com/content/aip/journal/jap/103/5/10.1063/1.2838491
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

SET electrical schematic. The island is separated from both source and drain electrodes with two tunnel junctions, which are characterized by their capacitances and and their resistances and . The island is controlled by a gate via its capacitance . Its total capacitance is and it carries a charge , which is integer times of the elementary charge (if there is no background charge ). When resistances are much higher than , the thermal energy is negligible compared to the charging energy .

Image of FIG. 2.
FIG. 2.

Representation of the charge states and the transition rates . Each transition rate is equal to the sum of two tunneling rates.

Image of FIG. 3.
FIG. 3.

Representation of the stability zones related to the charge states in the space. Each diamond-shaped thick dotted line delimits the set of stability zones related to the charge states . The area inside of the two oblique solid lines is the calculation zone, where every point of the space can be translated. Equations of these straight lines in the Cartesian coordinate system are . The combination of the two values determines the horizontal limits for .

Image of FIG. 4.
FIG. 4.

Example of translation of the working point from outside to inside the calculation zone. First, the drain voltage value determines the value of (here ). Then, the point is translated of integer times of along the direction, until it is inside the calculation zone, which is fixed, and the gate voltage value used in the calculation is determined as .

Image of FIG. 5.
FIG. 5.

Representation of the partition and calculation zone when is a half-integer. Equations of these straight lines in the Cartesian coordinate system are and .

Image of FIG. 6.
FIG. 6.

Representation of the final space partition: the number of states taking into account increases by one with each step of .

Image of FIG. 7.
FIG. 7.

verification of our model for symmetric device with , , and , at . Here symbols represent Monte Carlo simulation (CAMSET) (Ref. 12) and the solid line represents our model.

Image of FIG. 8.
FIG. 8.

verification of our model for symmetric device with , , and , at . Here symbols represent Monte Carlo simulation (CAMSET) (Ref. 12) and the solid line represents our model.

Image of FIG. 9.
FIG. 9.

verification of our model at different temperature levels for symmetric device with , , and . Here symbols represent Monte Carlo simulation (CAMSET) (Ref. 12) and the solid line represents our model.

Image of FIG. 10.
FIG. 10.

How the second gate bias could compensate the background charge effect. Here device parameters are , , and , at .

Image of FIG. 11.
FIG. 11.

Comparison of our model (solid line) with different implemented models (dotted line): (1) -limited model, (2) -limited model and (3) -limited model. Symbols represent CAMSET simulation. Here device parameters are , , , and , at .

Image of FIG. 12.
FIG. 12.

Comparison of our model (solid line) with a -limited model (dotted line) for a current biased SET. Symbols represent CAMSET simulation. Here device parameters are , , , and , at .

Image of FIG. 13.
FIG. 13.

Possible states and available transitions considered in the model when the spin degeneracy is (a) taken into account and (b) neglected.

Image of FIG. 14.
FIG. 14.

States and transitions considered when zero or one electron is allowed to enter the island in the models from: (a) Ref. 19, and (b) Ref. 20 (for one level available for tunneling).

Image of FIG. 15.
FIG. 15.

characteristics of a silicon-based SET having a 5 nm large island operating at and at , as simulated by (parabolic model not included): (1) our model, (2) model from Ref. 19, and (3) model from Ref. 20. Here model parameters are , , , and .

Image of FIG. 16.
FIG. 16.

characteristics of a silicon-based SET having a 5 nm large island operating at and at , as simulated by (parabolic model included): (1) our model, (2) model from Ref. 19, and (3) model from Ref. 20. Here model parameters are , , , , and .

Image of FIG. 17.
FIG. 17.

characteristics of a silicon-based SET having a 5 nm large island operating at and at with the parabolic barrier model as simulated by (parabolic model included): (1) our model, (2) model from Ref. 19, and (3) model from Ref. 20. Here model parameters are , , , , and .

Image of FIG. 18.
FIG. 18.

characteristics of a silicon-based SET having a 5 nm large island operating at and at different temperature levels as simulated by our model, including the parabolic barrier. Here model parameters are , , , , and .

Image of FIG. 19.
FIG. 19.

States and transitions considered when up to two electrons are allowed to enter the island: (a) in our model and (b) in the model in Ref. 20 (for two levels available for tunneling).

Image of FIG. 20.
FIG. 20.

characteristics of a silicon-based SET having a 5 nm large island operating at , as simulated by (parabolic model not included): (1) our model and (2) the model in Ref. 20 (for two levels accessible to up to two electrons). For reference, symbols represent results given by the model in Ref. 20 when one level is accessible to one electron. Here models parameters are , , and .

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/content/aip/journal/jap/103/5/10.1063/1.2838491
2008-03-10
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Voltage-limitation-free analytical single-electron transistor model incorporating the effects of spin-degenerate discrete energy states
http://aip.metastore.ingenta.com/content/aip/journal/jap/103/5/10.1063/1.2838491
10.1063/1.2838491
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