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Improved gate oxide integrity of strained Si -channel metal oxide silicon field effect transistors using thin virtual substrates
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10.1063/1.2917286
/content/aip/journal/jap/103/9/10.1063/1.2917286
http://aip.metastore.ingenta.com/content/aip/journal/jap/103/9/10.1063/1.2917286
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic of the thin virtual substrate layer structure.

Image of FIG. 2.
FIG. 2.

dc drain current vs drain voltage characteristics for the strained Si and Si control devices with gate lengths. The measurements were carried out at gate overdrive voltages of 1, 2, and 3 V.

Image of FIG. 3.
FIG. 3.

Effective electron mobility vs effective field for the strained Si and Si control devices. Both strained Si devices exhibit 100% mobility enhancements compared to bulk Si at high field.

Image of FIG. 4.
FIG. 4.

Initial gate leakage vs oxide electric field characteristics. Both strained Si MOSFETs exhibit a lower leakage compared to bulk Si, with further improvements for the thin virtual substrate strained Si device. Kinks in the characteristics for all of the devices are apparent at and differentiate between dominating leakage mechanisms and low and high.

Image of FIG. 5.
FIG. 5.

Capacitance -voltage characteristics for the strained Si and Si control devices.

Image of FIG. 6.
FIG. 6.

Experimental and simulated gate leakage characteristics: (a) Si control, (b) strained Si (thick virtual substrate), and (c) strained Si (thin virtual substrate). In all cases, the leakage is dominated by PF emissions followed by FN tunneling.

Image of FIG. 7.
FIG. 7.

(a) Characteristic PF plot of ln vs for the strained Si and Si control devices at 300 K. (b) Temperature dependence of PF emissions.

Image of FIG. 8.
FIG. 8.

Energy band diagrams illustrating Fowler–Nordheim (FN) tunneling, direct tunneling (DT), and Poole–Frenkel (PF) emissions.

Image of FIG. 9.
FIG. 9.

(a) Variation in ideal oxide tunneling currents with barrier height (virtual substrate Ge content). (b) Comparison of measured and modeled FN tunneling currents to bulk Si.

Image of FIG. 10.
FIG. 10.

AFM images showing an improved surface roughness for thin virtual substrates grown by using very low temperature growth. A cross-hatch morphology is observed only for the conventional thick virtual substrate.

Image of FIG. 11.
FIG. 11.

Midgap interface trap density vs rms roughness. increases with increasing surface roughness.

Image of FIG. 12.
FIG. 12.

High-field stressing at for the Si control MOSFETs: (a) stress-induced leakage current (SILC) as a function of stress time and (b) gate current vs oxide electric field at various stress times. The spikes in (a) are caused by the periodic removal of stress to evaluate vs characteristics in (b). Only a hard breakdown is evident.

Image of FIG. 13.
FIG. 13.

High-field stressing at for the strained Si MOSFETs fabricated on thick virtual substrates: (a) stress-induced leakage current (SILC) as a function of stress time and (b) gate current vs oxide electric field at various stress times. The increase in electrical noise after indicates the onset of soft breakdown.

Image of FIG. 14.
FIG. 14.

High-field stressing at for the strained Si MOSFETs fabricated on thin virtual substrates: (a) stress-induced leakage current (SILC) as a function of stress time and (b) gate current vs oxide electric field at various stress times. The increase in electrical noise at indicates the onset of soft breakdown.

Image of FIG. 15.
FIG. 15.

The 50% time and charge to hard breakdown and for the strained Si and Si control devices after stressing on the gate.

Image of FIG. 16.
FIG. 16.

Fractional increase in stress induced leakage current (SILC) vs normalized injection charge through the oxide when applying a stress. The fractional SILC increase for both strained Si devices is lower than that for the Si control.

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/content/aip/journal/jap/103/9/10.1063/1.2917286
2008-05-06
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates
http://aip.metastore.ingenta.com/content/aip/journal/jap/103/9/10.1063/1.2917286
10.1063/1.2917286
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