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Two-trap model for low voltage stress-induced leakage current in ultrathin SiON dielectrics
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10.1063/1.2969791
/content/aip/journal/jap/104/5/10.1063/1.2969791
http://aip.metastore.ingenta.com/content/aip/journal/jap/104/5/10.1063/1.2969791

Figures

Image of FIG. 1.
FIG. 1.

Poststress increase in gate current vs sense voltage at 298 K for NMOS and PMOS devices with 2.7 nm dielectrics. For both devices, the degradation is highest when the sense voltage approaches . After Nicollian, Ref. 9. © 1999 IEEE.

Image of FIG. 2.
FIG. 2.

Band diagram for tunneling in a metal-oxide- structure with applied. The possible transport paths are (1) tunneling of electrons from the metal gate into the VB, (2) tunneling of electrons from the metal gate into as-grown interface traps at the oxide- interface, followed by recombination with holes.

Image of FIG. 3.
FIG. 3.

Band diagram for PMOS at illustrating a two-trap LV-SILC process. Electrons tunnel from interface traps below the -well Fermi level into interface traps above the polysilicon Fermi-level. A steady-state current arises when electrons captured in polysilicon- interface traps recombine with majority holes in the polysilicon.

Image of FIG. 4.
FIG. 4.

Time zero NMOS terminal currents at 378 K.

Image of FIG. 5.
FIG. 5.

Time zero vs characteristics at 378 K both with and without the drain floating during the sweep.

Image of FIG. 6.
FIG. 6.

at 378 K with all terminals connected during the sense operation.

Image of FIG. 7.
FIG. 7.

at 378 K with all terminals connected during the sense operation.

Image of FIG. 8.
FIG. 8.

at 378 K with all terminals connected during the sense operation.

Image of FIG. 9.
FIG. 9.

Band diagrams for LV-SILC at for (a) tunneling processes between polysilicon and -well and (b) tunneling processes between polysilicon and NSD.

Image of FIG. 10.
FIG. 10.

Band diagrams for LV-SILC at for (a) tunneling processes between polysilicon and -well and (b) tunneling processes between polysilicon and NSD.

Image of FIG. 11.
FIG. 11.

Band diagrams for LV-SILC at for (a) tunneling processes between polysilicon and -well and (b) tunneling processes between polysilicon and NSD.

Image of FIG. 12.
FIG. 12.

Poststress NMOS terminal currents at 378 K. The time zero curves for this device are shown in Fig. 4.

Image of FIG. 13.
FIG. 13.

at 378 K with the -well floating during the sense operation.

Image of FIG. 14.
FIG. 14.

Poststress substrate current activation energy vs gate voltage both with and without the drain floating during the sense operation.

Image of FIG. 15.
FIG. 15.

Poststress gate current activation energy vs gate voltage both with and without the drain floating during the sense operation.

Image of FIG. 16.
FIG. 16.

at 378 K with the drain floating during the sense operation.

Image of FIG. 17.
FIG. 17.

Band diagram for LV-SILC at for tunneling processes between polysilicon and -well. The origin of electrons in the -well CB is BTBT in the -well space charge region.

Tables

Generic image for table
Table I.

Summary of the NMOS interface trap peaks sensed by LV-SILC in each device terminal.

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/content/aip/journal/jap/104/5/10.1063/1.2969791
2008-09-10
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Two-trap model for low voltage stress-induced leakage current in ultrathin SiON dielectrics
http://aip.metastore.ingenta.com/content/aip/journal/jap/104/5/10.1063/1.2969791
10.1063/1.2969791
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