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Resistance switching and retention behaviors in polycrystalline La-doped ceramics chip devices
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10.1063/1.2975316
/content/aip/journal/jap/104/5/10.1063/1.2975316
http://aip.metastore.ingenta.com/content/aip/journal/jap/104/5/10.1063/1.2975316

Figures

Image of FIG. 1.
FIG. 1.

(a) Optical microscope cross-section image and (b) schematic device structure of the fabricated device.

Image of FIG. 2.
FIG. 2.

Typical characteristics after the forming process plotted on (a) linear and (b) semilogarithmic current scales.

Image of FIG. 3.
FIG. 3.

Resistance switching behavior by applying voltage pulses of with duration of 100 ms. The open circles represent the resistance and open squares represent the switching and read voltages.

Image of FIG. 4.
FIG. 4.

(a) Schematic band structure in La-doped ceramics, (b) equivalent circuit model, and (c) typical complex impedance plane plots in HRS and LRS. Open circles and squares represent the impedance spectra of the HRS and LRS, respectively. The inset shows the impedance spectra of the HRS and LRS in the high-frequency region.

Image of FIG. 5.
FIG. 5.

Measurement result of on/off switching endurance test. (a) shows the voltage protocol in the on/off switching endurance test. Five dc voltage pulses of with of 100 ms are applied between the outer electrodes, and then the resistance is estimated at . (b) shows the on/off resistance switching behavior vs on/off cycling number. The open circle represents the resistance of devices estimated at after the application of switching voltage pulses.

Image of FIG. 6.
FIG. 6.

Resistance retention properties in HRS and LRS at room temperature. (a) shows the voltage protocol in measurements. Five dc voltage pulses of with of 100 ms are applied between the outer electrodes to switch the devices to the HRS or LRS, and then the resistance is estimated every 10 s for . Upper and bottom sections indicate the measurements in the LRS and HRS, respectively. (b) shows the measurement results. The open circles and squares represent the resistance of HRS and LRS, respectively.

Image of FIG. 7.
FIG. 7.

Temperature dependences of the resistance retention properties and resistance from room temperature to . (a) shows the characteristics at various temperatures. The solid lines represent the resistance in the HRS and open symbols represent the resistance in the LRS. (b) shows the temperature dependency of the initial resistance after resistance switching. The open circles and squares indicate the resistance of the LRS and HRS, respectively.

Image of FIG. 8.
FIG. 8.

Schematic band structures of DSB at grain boundaries. (a) and (b) represent the DSB without and under the dc biasing. (c) represents the DSB after removing the dc biasing.

Image of FIG. 9.
FIG. 9.

Schematic band structures of DSB based on the proposed mechanism of resistance switching and memory effects in this study. (a) represents the initial state of DSB and (b) represents the DSB during the forming process with extremely high dc biasing. (c) and (d) represent the change in the DSB’s height and space-charge distribution derived from trapped electrons at interface states and oxygen vacancies in LRS and HRS, respectively.

Tables

Generic image for table
Table I.

Resistance, electrical nonlinearity , and resistance change values.

Generic image for table
Table II.

Summary of values obtained for electric parameters corresponding to the equivalent circuit model (Fig. 4 used in the fitting processes of the measured data in HRS and LRS).

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/content/aip/journal/jap/104/5/10.1063/1.2975316
2008-09-08
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Resistance switching and retention behaviors in polycrystalline La-doped SrTiO3 ceramics chip devices
http://aip.metastore.ingenta.com/content/aip/journal/jap/104/5/10.1063/1.2975316
10.1063/1.2975316
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