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Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors
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Image of FIG. 1.
FIG. 1.

Process simulation flow for silicon channel transistor on SOI substrate with stressors in source and drain regions. The conventional process flow uses silicon source and drain recess followed by selective epitaxial growth of stressors. The germanium condensation process involves selective epitaxial growth of followed by germanium condensation thermal step.

Image of FIG. 2.
FIG. 2.

Illustration of crystal lattices in the vicinity of the vertical and horizontal heterojunctions formed by stressors and silicon channel with arrows indicating the nature of the stresses experienced by the crystal lattices. At the vertical heterojunction, the silicon region has a vertical tensile strain component, and at the horizontal heterojunction, the silicon region immediately underlying the stressor has a horizontal tensile strain component.

Image of FIG. 3.
FIG. 3.

Schematic of source and drain transistor obtained after process simulation. The notations for key design parameters are shown in the figure. The gate length is denoted by , source and drain length is denoted by , total thickness of stressor is labeled as , and the recess depth is denoted by .

Image of FIG. 4.
FIG. 4.

Compressive lateral strain component averaged along the channel at a depth of 2 nm below the gate oxide interface. The strain enhancement due to source and drain stressors increases with SOI thickness scaling.

Image of FIG. 5.
FIG. 5.

Compressive lateral strain in the channel induced by raised source and drain stressors. The contribution of raised source and drain toward compressive strain saturates in UTB (5 nm) SOI transistors.

Image of FIG. 6.
FIG. 6.

Strain saturation observed in the channel by increasing the length of source and drain stressors in thin body SOI transistors.

Image of FIG. 7.
FIG. 7.

Compressive lateral strain enhancement in the channel after embedding the stressors upto the buried oxide interface using germanium condensation process flow. The available thickness of stressors was reduced with SOI scaling but strain enhancement resulted presumably from lesser strain relaxation in UTB isolated transistors.

Image of FIG. 8.
FIG. 8.

Required germanium concentration in source and drain stressors to maintain 1% compressive lateral strain in the channel. The germanium content requirements are reduced in UTB transistors.

Image of FIG. 9.
FIG. 9.

Strain enhancement with gate length scaling demonstrates scalability of germanium condensation approach to a gate length of 10 nm on UTB SOI substrate.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors