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Study of surface passivation of strained indium gallium arsenide by vacuum annealing and silane treatment
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Image of FIG. 1.
FIG. 1.

High resolution XRD rocking curve of the (004) reflection on the structure. The high crystalline quality of the structure is confirmed by the clear interference pattern (Pendellösung oscillations) in the rocking curve.

Image of FIG. 2.
FIG. 2.

AFM images of (a) GaAs before MOCVD or III-V growth, showing an excellent rms surface roughness of . (b) After the growth of on GaAs, the rms surface roughness is . The surface roughness can be maintained during the MOCVD III-V epitaxy process. A smooth surface is necessary to avoid any undesirable degradation of effective carrier mobility in surface channel transistors due to surface roughness scattering.

Image of FIG. 3.
FIG. 3.

The thicknesses of native oxide on InGaAs after HCl, , and cleaning steps as a function of air exposure durations. The thicknesses were monitored at 0, 5, and 10 min after cleaning. The air exposure interval between different cleaning steps should be minimized due to rapid growth of native oxide in atmosphere. VA at should be employed to remove the remaining native oxide after wet cleaning.

Image of FIG. 4.
FIG. 4.

(a) Arsenic (As) XPS spectra show the significant reduction in As–O bond after VA and treatment, contributing to the improved device characteristics. (b) spectra verify the existence of Si–O bond at the interface in the samples with VA and passivation, indicating the thin silicon interfacial layer was oxidized.

Image of FIG. 5.
FIG. 5.

HRTEM micrographs showing the cross section of a completed TaN/HfAlO/InGaAs stack (a) without and (b) with VA and passivation. In the samples with VA and treatment, an oxidized silicon layer was observed. Diffractogram in the inset reveals excellent crystalline quality of the strained layer.

Image of FIG. 6.
FIG. 6.

(a) characteristics of TaN/HfAlO/InGaAs MOS capacitors characterized at frequencies of 10 kHz, 100 kHz, and 1 MHz. Drastic reduction in frequency dispersion was found in the capacitors with VA and passivation. (b) Significant reduction in hysteresis can also be realized in forward and reverse sweeps through the integration of VA and treatment during gate stack formation.

Image of FIG. 7.
FIG. 7.

(a) Hysteresis vs treatment temperature ranging from 300 to . (b) Interface state densities at various treatment temperatures. as low as can be achieved with VA and treatment.

Image of FIG. 8.
FIG. 8.

The gate leakage current density obtained at as a function of EOT. With EOT of 2.3 nm, the InGaAs MOS capacitor demonstrates a low of at .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Study of surface passivation of strained indium gallium arsenide by vacuum annealing and silane treatment