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Highly uniform resistive switching characteristics of memory devices
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) The schematic structure of the designed memory stack; (b) The cross-sectional structure SEM image of the memory cell stack.

Image of FIG. 2.
FIG. 2.

The typical bipolar current vs voltage curve of the fabricated memory cell.

Image of FIG. 3.
FIG. 3.

The cycling endurance of the cell in the dc sweep mode. The resistance measured at 0.3 V read voltage is dispersion.

Image of FIG. 4.
FIG. 4.

(a) The cycling endurance of the cell in pulse sweep mode. The applied pulse is for the set process and for the reset process, respectively.

Image of FIG. 5.
FIG. 5.

The cumulative probability of and of the memory devices under dc sweep and pulse sweep modes.

Image of FIG. 6.
FIG. 6.

Distribution of the set and reset voltages in the case of the dc sweep.

Image of FIG. 7.
FIG. 7.

Retention characteristics of measured at room temperature.

Image of FIG. 8.
FIG. 8.

Retention characteristics of memory cell in HRS under different sampling voltage stresses.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Highly uniform resistive switching characteristics of TiN/ZrO2/Pt memory devices