(a) The schematic structure of the designed memory stack; (b) The cross-sectional structure SEM image of the memory cell stack.
The typical bipolar current vs voltage curve of the fabricated memory cell.
The cycling endurance of the cell in the dc sweep mode. The resistance measured at 0.3 V read voltage is dispersion.
(a) The cycling endurance of the cell in pulse sweep mode. The applied pulse is for the set process and for the reset process, respectively.
The cumulative probability of and of the memory devices under dc sweep and pulse sweep modes.
Distribution of the set and reset voltages in the case of the dc sweep.
Retention characteristics of measured at room temperature.
Retention characteristics of memory cell in HRS under different sampling voltage stresses.
Article metrics loading...
Full text loading...