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Effect of simultaneous source and bias pulsing in inductively coupled plasma etching
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10.1063/1.3262616
/content/aip/journal/jap/106/10/10.1063/1.3262616
http://aip.metastore.ingenta.com/content/aip/journal/jap/106/10/10.1063/1.3262616

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic of the ICP reactor used to investigate impact of simultaneous source and bias pulsing. (b) Schematic of the pulse power waveform. The base case pulse frequency is with a pulse ramp-up and -down time of . IEADs corresponding to the bias power pulse will be characterized during each of the five distinct phases identified.

Image of FIG. 2.
FIG. 2.

Spatially averaged plasma properties as a function of time for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) and duty cycles of 25%–75%: (a) density, (b) density, and (c) electron temperature.

Image of FIG. 3.
FIG. 3.

Spatially averaged plasma properties as a function of time for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) and duty cycles of 25%–75%: (a) , (b) , and (c) densities.

Image of FIG. 4.
FIG. 4.

Electron density for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) and duty cycle of 50% at different times during the pulse. Results are shown for (a) and (b) during the ramp-up phase; (c) , (d) , and (e) during the top-flat phase; (f) when the power is turned off; (g) and (h) during the “off-1” phase; and (i) and (j) during the “off-2” phase. (Densities are plotted using a log scale over 2 decades. The color bar shows the range of the contours relative to the maximum value.) (enhanced online). [URL: http://dx.doi.org/10.1063/1.3262616.1]10.1063/1.3262616.1

Image of FIG. 5.
FIG. 5.

IEADs, averaged over the wafer, for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) during each distinct phase of the pulse cycle as a function of duty cycle: (a) 25%, (b) 50%, and (c) 75%. IEADs are plotted using a log scale over 2 decades.

Image of FIG. 6.
FIG. 6.

Temporal dynamics of the rf bias voltage and self-generated dc bias to deposit the peak bias power for the base case conditions (, , , peak ICP power, pulse frequency) for different duty cycles: (a) 25%, (b) 50%, and (c) 75%.

Image of FIG. 7.
FIG. 7.

Electron and ion fluxes to the wafer as a function of time for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) for different duty cycles: (a) 25%, (b) 50%, and (c) 75%. is the major ion due to higher rates of charge exchange from .

Image of FIG. 8.
FIG. 8.

Final predicted etch profiles for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) and duty cycles of 25%–100%. The features were etched for a fixed processing time.

Image of FIG. 9.
FIG. 9.

IEADs, averaged over the wafer, for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) during each distinct phase of the pulse cycle as a function of the pulse ramp time for a duty cycle of 50%: (a) , (b) , and (c) . These figures use a log scale plotted over 2 decades.

Image of FIG. 10.
FIG. 10.

Time variation of the rf bias voltage and self-generated dc bias to deposit the peak bias power for the base case conditions (, , , peak ICP power, pulse frequency) as a function of the pulse ramp time for a duty cycle of 50%: (a) , (b) , and (c) .

Image of FIG. 11.
FIG. 11.

Electron and ion fluxes to the wafer as a function of time for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% and different pulse ramp times: (a) , (b) , and (c) .

Image of FIG. 12.
FIG. 12.

Final predicted etch profiles for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% and pulse ramp times of .

Image of FIG. 13.
FIG. 13.

Time variation of the rf bias voltage and self-generated dc bias for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% as a function of the source and bias power pulse phase lags: (a) 90°, (b) 180°, and (c) 270°.

Image of FIG. 14.
FIG. 14.

IEADs, averaged over the wafer, for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% during each distinct phase of the pulse cycle as a function of phase lags: (a) 90°, (b) 180°, and (c) 270°. All phases are referenced to the beginning of the bias-on period. IEADs are plotted using a log scale over 2 decades.

Image of FIG. 15.
FIG. 15.

Electron and ion fluxes to the wafer as a function of time for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% for different phase lags between the source and bias power pulses: (a) 90°, (b) 180°, and (c) 270°.

Image of FIG. 16.
FIG. 16.

Final predicted etch profiles for the base case conditions (, , , peak ICP power, peak bias power, pulse frequency) at a duty cycle of 50% and phase lags of 90°–270°. The features were etched for a fixed processing time.

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/content/aip/journal/jap/106/10/10.1063/1.3262616
2009-11-30
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effect of simultaneous source and bias pulsing in inductively coupled plasma etching
http://aip.metastore.ingenta.com/content/aip/journal/jap/106/10/10.1063/1.3262616
10.1063/1.3262616
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