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Thermal excitation of large charge offsets in a single-Cooper-pair transistor
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10.1063/1.3266012
/content/aip/journal/jap/106/12/10.1063/1.3266012
http://aip.metastore.ingenta.com/content/aip/journal/jap/106/12/10.1063/1.3266012
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

SEM micrograph showing (i) the SET source (S) and drain (D) electrodes and island, (ii) the gate electrodes (G1 and G2). The contrast has been increased in the central region to show the Al electrodes. The source, drain, and gate leads are covered by a metallic Au ground plane on the upper and lower parts of the image.

Image of FIG. 2.
FIG. 2.

The characteristic of the SET, showing the Cooper-pair peak (C), the JQP peak (J), and the quasiparticle branch.

Image of FIG. 3.
FIG. 3.

CBO at 15 mK for up (◼) and down (●) gate sweeps (a) at the JQP peak (, lower trace) showing periodicity and (b) at the Cooper-pair peak (, upper trace) showing periodicity. The data show a hysteretic transition into a trapped charge state with . The axes have been offset for clarity. The arrows show the voltage sweep directions.

Image of FIG. 4.
FIG. 4.

The offset charge vs gate voltage observed using periodic CBO, showing the large charge offsets, .

Image of FIG. 5.
FIG. 5.

Hysteresis in the CBO current while sweeping the gate voltage at 242 mK. The transition voltages for electron capture and escape and show a range of values. The vertical axis for each trace is offset for clarity.

Image of FIG. 6.
FIG. 6.

Scatter plots of 1000 individual sweeps for an electron capture/escape pair at 25, 100, and 250 mK refrigerator temperatures. Each point shows the voltages and and the hysteresis at which the jumps occurred for a single sweep.

Image of FIG. 7.
FIG. 7.

Probability plots of the initial state at refrigerator temperatures of 242, 200, 165, 116, 100, 50, 45, and 25 mK refrigerator temperatures. (a) Sweeping the gate positive, (electron capture). The plots are offset along the axis for clarity, with the 25 mK plot on the right and the 242 mK plot on the left. (b) Sweeping the gate negative, (electron escape). The plots are offset along the axis for clarity, with the 25 mK plot on the left and the 242 mK plot on the right.

Image of FIG. 8.
FIG. 8.

The relaxation times for electron capture (◼) and escape (●) below 250 mK.

Image of FIG. 9.
FIG. 9.

Typical exponential decays after switching a gate voltage from stable to a metastable voltage, repeated 1000 times, at 25 mK refrigerator temperature. Two data sets are shown, for electron escape and electron capture . The inset shows the source–drain current vs time. At , the gate voltage is switched from a stable to a metastable voltage. The change in due to charge transfer is delayed. Nine data sets are shown at a 25 mK refrigerator temperature.

Image of FIG. 10.
FIG. 10.

The measured relaxation rate when switching a gate voltage rapidly from a stable voltage (in region A) to a metastable voltage, at 25 mK refrigerator temperature. The voltages and show the threshold voltages when sweeping the gate voltage slowly. When the gate voltage is swept quickly, the relaxation time changes abruptly at and .

Image of FIG. 11.
FIG. 11.

The relaxation time for (a) electron escape and (b) electron capture at 25 mK refrigerator temperature.

Image of FIG. 12.
FIG. 12.

The relaxation time for (a) electron escape and (b) electron capture at 242 mK.

Image of FIG. 13.
FIG. 13.

The ratio of the escape time to the capture time vs the voltage for and for . The solid line shows the fit to Eq. (5).

Image of FIG. 14.
FIG. 14.

[(a) and (d)] for electron capture and escape transitions at 25 and 165 mK refrigerator temperatures, showing fits to Eq. (6). [(b) and (e)] for electron capture and escape transitions at 25 and 165 mK on a logarithmic scale, showing fits to Eq. (6) and the exponential decay beyond the transition. [(c) and (f)] for electron capture and escape transitions at 25 and 165 mK, showing the thermal excitation before the threshold.

Image of FIG. 15.
FIG. 15.

The parameter vs the refrigerator temperature for electron escape (◼ and ●) and electron capture (◻ and ○). The lines show (solid) and [(dashed, allowing for heating (Ref. 36)] for .

Image of FIG. 16.
FIG. 16.

(a) Schematic model of a TLF coupled to an electron trap. (b) The excitation energies and versus the gate voltage . The voltages and show the threshold voltages when sweeping the gate voltage slowly. When the gate voltage is swept quickly, the relaxation time changes abruptly at and .

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/content/aip/journal/jap/106/12/10.1063/1.3266012
2009-12-17
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Thermal excitation of large charge offsets in a single-Cooper-pair transistor
http://aip.metastore.ingenta.com/content/aip/journal/jap/106/12/10.1063/1.3266012
10.1063/1.3266012
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