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Fault-tolerance and thermal characteristics of quantum-dot cellular automata devices
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10.1063/1.3428453
/content/aip/journal/jap/107/11/10.1063/1.3428453
http://aip.metastore.ingenta.com/content/aip/journal/jap/107/11/10.1063/1.3428453

Figures

Image of FIG. 1.
FIG. 1.

The QCA cells represent (a) the geometry of a cell and (b) the polarized state for a binary logic 1 and 0 configuration (Refs. 1 and 2).

Image of FIG. 2.
FIG. 2.

(a) Ideal locations for dot 1 and 5. (b) Displaced position for dot 1.

Image of FIG. 3.
FIG. 3.

The simulation results for the binary wire (a) cell layout of a binary wire and (b) success rate vs DF.

Image of FIG. 4.
FIG. 4.

The simulation results for the inverter chain (a) cell layout of an inverter chain and (b) success rate vs DF.

Image of FIG. 5.
FIG. 5.

The simulation results for the inverter (a) the cell layout and (b) success rate vs DF.

Image of FIG. 6.
FIG. 6.

The simulation results for the AND gate (a) the cell structure and (b) success rate vs DF.

Image of FIG. 7.
FIG. 7.

The simulation results for OR gate (a) the cell layout and (b) success rate vs DF.

Image of FIG. 8.
FIG. 8.

The simulation results for a crossover. (a) The cell layout and (b) success rate vs DF.

Image of FIG. 9.
FIG. 9.

The XOR layout (Ref. 2).

Image of FIG. 10.
FIG. 10.

(a) Success rate vs DF for the XOR gate with 00 input (b) success rate versus DF for the XOR gate with 10 input (Ref. 49).

Image of FIG. 11.
FIG. 11.

Basic QCA devices and XOR (a) success rate vs DF at 0 K, (b) BDF vs temperatures (Ref. 49).

Tables

Generic image for table
Table I.

Breakdown DFs for QCA devices at different temperatures.

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/content/aip/journal/jap/107/11/10.1063/1.3428453
2010-06-02
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Fault-tolerance and thermal characteristics of quantum-dot cellular automata devices
http://aip.metastore.ingenta.com/content/aip/journal/jap/107/11/10.1063/1.3428453
10.1063/1.3428453
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