(a) HRTEM image of dielectric layer (21.2 nm). The inset shows schematic of a MOS device structure. (b) EOT vs thickness of dielectric layer. The inset shows a series of C-V characteristics.
(a) Schematic of a ZnO nanowire FET device structure. (b) Scanning electron microscopy image of a single ZnO nanowire connected between source and drain electrodes in a FET device. (c) A series of characteristics for ZnO nanowire FETs with varying dielectric thicknesses (21.2, 49.6, and 78.3 nm).
(a) Leakage current density vs applied voltage through dielectric layers of different thicknesses (21.2, 49.6, and 78.3 nm) and a 12 nm layer. (b) vs 1/V plot for and 12 nm dielectric layers. Inset is a zoomed-in plot near the transition voltages (marked by arrows) from DT to FN tunneling (see text in detail).
(a) characteristics for ZnO nanowire FETs with varying dielectric thicknesses at fixed . The inset shows the statistical distribution of the measured threshold voltage. (b) Transconductance and mobility of ZnO nanowire FETs with varying dielectric thicknesses.
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