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Ultra-low-power superconductor logic
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View: Figures


Image of FIG. 1.
FIG. 1.

(Color) A Reciprocal Quantum Logic (RQL) shift register. (a) Novel reciprocal data encoding, where the ac clock propagates digital ones as pairs of single flux quantum (SFQ) pulses of opposite polarity. (b) Schematic of the RQL shift register bit. Cross-wired transformers effectively produce a four-phase clock with only two ac power lines, in quadrature. The SFQ pulses are shown as loop currents that move through the circuit with a half cycle of separation. The circuit parameters are mA, mA, pH, pH, pH, pH, and  = 0.7 mA amplitude and 0.2 mA effective offset (not shown). (c) Physical layout of the shift register in a fabrication process with four Nb metal layers, with the middle layers used for inductive wireup, and the top and bottom layers serving as ground plane shields. The ac clock lines, and a separate line to apply dc offset, are microstrips with the filament in a first metal layer and ground in the top layer. Bias inductors lie in the third metal layer, situated on top of the clock signal line, with strong inductive coupling scaling linearly with the length of the transformer.

Image of FIG. 2.
FIG. 2.

Power dissipation. The power ratio of the clock output for the two data patterns, corresponding to all “ones” and all “zeros,” was measured for frequencies of 2 to 12 GHz. The power dissipation is derived from the directly observed power ratio and the on-chip clock power of 12.5 , calculated as the geometric mean of applied and returned power. At 6 GHz and below, the measurement error is within the size of the data points. At 8 GHz and above, the primary source of error is variation in the clock attenuation on the different lines in the American Cryoprobe BCP-2 chip holder, producing a visible spread between the data points for clock 1 and clock 2. Additional data points correspond to a 6 pseudorandom input pattern that shows half the power dissipation as compared to that of all “ones,” as expected. The measured power dissipation agrees well with the result from the circuit simulation, , with a single multiplicative fitting parameter. However, the power is three times smaller than the analytical estimate that scales with circuit size and frequency as and which would apply to dc-powered SFQ devices.

Image of FIG. 3.
FIG. 3.

(Color) RQL logic gates. The logic gates AnotB and AndOr are simple and robust due to the reset function implicit in reciprocal data encoding. (a), (b) Block diagram, pulse logic behavior, and schematic of the AnotB gate. The operation of the gate is based on a high-efficiency transformer that is cross-wired to invert the polarity of the signal from input B. The schematic values are mA, mA, pH, pH, pH, pH, pH, and mA. (c) In the physical layout, the high efficiency transformer is implemented using moats in the upper and lower ground planes, which appear as seven horizontal traces cutting across the vertical wires. (d), (e) Block diagram, pulse logic description, and schematic of the AndOr gate. Here the high-efficiency transformers aid the propagation of either input pulse to the outputs, but they inhibit propagation to the opposite input. The schematic values are pH, pH, pH, pH, pH, pH, pH, and mA amplitude and 0.2 mA offset.

Image of FIG. 4.
FIG. 4.

(Color) RQL logic test. (a) The circuit has two inputs, three logic gates, and four logic outputs including a synthesized XOR. Fanout is produced using an interconnect consisting of two-junction shift register stages. (b) The complete circuit includes input gates that convert a return-to-zero (RZ) waveform to RQL data encoding and on-chip output amplifiers that convert signals back to RZ voltage levels. The clock and data inputs are inductively coupled to the circuit and return on another set of signal lines without contacting chip ground, which contributes to the high signal integrity at GHz rates. (c) Input and output waveforms at 6 Gb/s were captured on a sampling oscilloscope. A 1023-bit pseudorandom pattern was split and applied to the inputs with a 39 bit offset. No signal averaging, smoothing, or subtraction was used in the measurement.

Image of FIG. 5.
FIG. 5.

Bit-error rate (BER). The BER of the AnotB gate at 6 GHz is shown as a function of its flux bias . A 32-bit input pattern generated with an Anritsu MP1763 C was split and applied to the inputs with a 15 bit relative shift, and the XOR output was compared to the correct pattern with an Anritsu MP1764 C error detector. The error bars on the lowest points correspond to counting statics of 4 errors (left) and 5 errors (right). Near the center, no errors detected for a period of 30 h gives an error floor below for the entire circuit. The data fitted to the error function extrapolate to a minimum BER of at the optimal bias of 1.82 mA. Additional curves correspond to the BER scaled for reduced device size and power.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Ultra-low-power superconductor logic