1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Intrinsic and doped coupled quantum dots created by local modulation of implantation in a silicon nanowire
Rent:
Rent this article for
USD
10.1063/1.3581122
/content/aip/journal/jap/109/8/10.1063/1.3581122
http://aip.metastore.ingenta.com/content/aip/journal/jap/109/8/10.1063/1.3581122

Figures

Image of FIG. 1.
FIG. 1.

(Color online) (a) TEM cross-view of a typical triple gate sample before spacer deposition. The gate length is 40nm and the spacing between gates is 40nm. (b) SEM top-view of a typical double gate sample after spacers are formed all around the gates. The silicon nanowire is completely covered from source to drain. (c), (d), (e), (i) Schematic cross-views of different kinds of two-gate samples. The doping of the silicon nanowire is indicated with gray levels. V < 0 indicates depletion gates used to create tunnel barriers. V > 0 indicates gates used to accumulate electrons. (c) A-type: without LDD implantation. (d) B-type: with LDD implantation. (e) C-type: with small spacers. (f), (g), (h) Longitudinal band structures and equivalent single-electron circuits corresponding to (c), (d) and (e) when no voltage is applied on the substrate. (f) A double dot is created by accumulation of carriers below the two gates (see Ref. 15). (g) A dot is created by implantation of Arsenic dopants between the gates. Its coupling to the electrodes is tuned by the two top gates. (h) A triple dot is created (Ref. 15) both by accumulation of carriers below the gates and implantation of arsenic dopants between them. (i) Alternative design with two levels of gates (10,11) (an upper and two top gates) and no implantation of the silicon nanowire (Refs. 10 and 11).

Image of FIG. 2.
FIG. 2.

(Color online) Drain-source conductance of two double gate samples vs V g1 at room temperature and 4.2K. V g2 = 3D1.2 V, thus conductance is determined by the region below gate 1. Sample 1 (type A). Regular CBO are observed at 4.2K due to the formation of a dot below gate 1 and tunneling of electrons through the undoped nanowires located below the spacers (Refs. 13 and 15). Sample 2 (type B). No CBO is observed. Inset: detail at 4.2K in linear scale.

Image of FIG. 3.
FIG. 3.

(Color online) Color plot of the drain-source conductance vs Vg 1 and Vg 2 at 4.2K for two nominally identical double gate samples. (a) Sample 3 (type A). Hexagons (barely seen at 4.2K, see also Ref. 15) are observed above threshold. (b) Sample 4 (type B). CBO are periodic in (Vg 1 + Vg 2). Period of CBO is 10mV ± 1mV and does not depend on gate voltages as expected for a strongly doped electron island located between the gates. The onset of the current is at negative gate voltages because of the shortening of the electrical gate length due to dopant diffusion.

Image of FIG. 4.
FIG. 4.

(Color online) Drain-source conductance vs Vg1 at various Vg2 at 4.2K for sample 4. From bottom to top: Vg2 = −700 mV, −550 mV, −150 mV, 250mV. For low Vg2 the current is limited mainly by barrier 2 tunnel conductance. At large Vg2 CBO are suppressed by strong coupling to the drain through barrier 2. The enveloping structure is due to gate modulation of the tunneling transmission under gate 1. The shift toward positive Vg1 with decreasing Vg2 due to the cross talking between gates has been substracted.

Image of FIG. 5.
FIG. 5.

(Color online) Color plot of the drain-source conductance vs Vg 1 and Vg 2 at 4.2K for two samples without LDD. A strong positive voltage is applied on the substrate. (a) Sample 5 with large spacers (type A), VB  = 20 V. The positive substrate bias increases the conductance of the intrinsic silicon as LDD doping does for B-type samples. At negative Vg 1 and Vg 2, a single dot and tunnel barriers separating it from source and drain are created. (b) Sample 6 with small spacers (type C), VB  = 12.64 V. In both cases CBO are periodic in (Vg 1 + Vg 2). The period of CBO is approx. twice as large in (a) than in panel (b) due to different sample width. The concentration of electrons in the central dot either by chemical (b) or electrostatic doping (a) is large. Thus the period of CBO is independent on gate voltages. Conductance is higher in panel (a) because it is measured well above threshold, whereas, in panel (b) it is measured just above threshold.

Image of FIG. 6.
FIG. 6.

(Color online) Color plot of the drain-source conductance at 4.2K in sample 7 with three gates and with LDD implantation (type B) [See Fig. 1(a)]. The panels correspond to different voltages Vg 3 applied to the central gate. Vg 1 and Vg 2 are both strongly negative so that two dots are formed between gates 1 and 3 and gates 2 and 3. Dashed lines are guides for the eyes. (a) Capacitance coupling between the two dots is negligible. The points at which both dots are non-blockaded are on a square lattice. The lines joining these points are due to cotunneling. (b) Inter-dot capacitive coupling is increased. The points on the square lattice are extended along the diagonal. (c) A clear honeycomb pattern is observed, characteristic of a strongly capacitively coupled double dot system. (d) The antidiagonal pattern of lines indicates the formation of a single large dot.

Tables

Generic image for table
Table I.

Properties of the samples compared in the article. The spacer length and whether LDD is performed determine the sample type. Samples {1, 2} and {3, 4, 5} are nominally identical apart from LDD implantation.

Loading

Article metrics loading...

/content/aip/journal/jap/109/8/10.1063/1.3581122
2011-04-28
2014-04-17
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Intrinsic and doped coupled quantum dots created by local modulation of implantation in a silicon nanowire
http://aip.metastore.ingenta.com/content/aip/journal/jap/109/8/10.1063/1.3581122
10.1063/1.3581122
SEARCH_EXPAND_ITEM