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Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation
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10.1063/1.3662144
/content/aip/journal/jap/110/10/10.1063/1.3662144
http://aip.metastore.ingenta.com/content/aip/journal/jap/110/10/10.1063/1.3662144
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Current density vs voltage for NH4OH, (NH4)2 S, or UV–S bonded GaAs/GaAs, and reference GaAs with AuGe/Ni/Au contacts on front and back: (a) annealed for 2 h at 400 °C, and (b) after additional rapid thermal processing at 600 °C for 2 min.

Image of FIG. 2.
FIG. 2.

HRTEM of GaAs/GaAs interface annealed 2 h at 400 °C treated with (a) UV–S, and (b) (NH4)2S.

Image of FIG. 3.
FIG. 3.

HRTEM of UV–S GaAs/GaAs interface annealed 2 h at 400 °C plus a 1-min rapid thermal anneal at 600 °C.

Image of FIG. 4.
FIG. 4.

STEM image under Z-contrast conditions of GaAs/GaAs interface after 1-min 600 - °C rapid thermal anneal for (a) UV–S, and (b) NH4OH treatment.

Image of FIG. 5.
FIG. 5.

Zero-bias dc conductance of wafer-bonded n-GaAs/n-GaAs vs inverse measurement temperature for samples that received 2-h 400- °C anneal plus 2-min RTA at 600 °C and the fitting of Eq. (1) to the data.

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/content/aip/journal/jap/110/10/10.1063/1.3662144
2011-11-22
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation
http://aip.metastore.ingenta.com/content/aip/journal/jap/110/10/10.1063/1.3662144
10.1063/1.3662144
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