1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer
Rent:
Rent this article for
USD
10.1063/1.3672448
/content/aip/journal/jap/110/12/10.1063/1.3672448
http://aip.metastore.ingenta.com/content/aip/journal/jap/110/12/10.1063/1.3672448

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Schematic of (a) a conventional PCRAM cell, and (b) a multi-level PCRAM cell fabricated in this work. (c) TEM image of the Ta2O5 barrier layer sandwiched between the NGST and undoped GST layers in the multi-level PCRAM cell.

Image of FIG. 2.
FIG. 2.

(Color online) Resistance-Time plot demonstrating the three distinct multi-level resistance states for one particular PCRAM device. The states are denoted as State I, State II, and State III. The horizontal dashed lines indicate the resistance levels of the respective states. The Reset and Set pulses used to trigger the switching of states in the cell are denoted by the arrows. Resistance values are regularly sampled or read in between switching events.

Image of FIG. 3.
FIG. 3.

Retention characteristics of a multi-level PCRAM device. The measurements were done at room temperature and pressure. The device used to obtain the data was the same as that shown in Fig. 2. The pulsing conditions used to program the device in a certain state are annotated in the figure.

Image of FIG. 4.
FIG. 4.

(a) Distribution of pulse voltages, and (b) distribution of pulse durations used for the respective Set and Reset pulses. Both distributions show the optimal switching conditions of all 18 working devices tested in this work. The tight distributions of the pulse voltages and durations show good uniformity.

Image of FIG. 5.
FIG. 5.

Resistance-Voltage curve for a PCRAM device (different from the one in Fig. 2) showing the Set and Reset operations using a fixed pulse width of 800 ns. The device was initialized to the completely amorphous state (State III) before each pulse and read operation.

Image of FIG. 6.
FIG. 6.

Distribution of resistance values for each state, for a set of 10 measured devices [including the device shown in Fig. 4]. This set of devices has undergone the Resistance-Voltage pulse testing.

Image of FIG. 7.
FIG. 7.

(Color online) DC I-V sweep of a particular multi-level PCRAM device. The straight lines denote the different gradients corresponding to each multi-level state. The change in gradients are indicated by the dashed lines.

Image of FIG. 8.
FIG. 8.

(Color online) (a) Temperature profile plot and (b) temperature contour plot of a simulated device undergoing the 1st Reset Pulse. The pulsing condition used was 10 ns 4 V. The temperature profile plot was extracted at nodes with the peak temperature in the NGST (circle) and GST (square) layers respectively.

Image of FIG. 9.
FIG. 9.

(Color online) Temperature profile plot of a simulated device undergoing the Intermediate Crystallization Pulse. The pulsing condition used was 400 ns 1 V. The temperature profile plot was extracted at nodes with the peak temperature in the NGST (circle) and GST (square) layers respectively.

Image of FIG. 10.
FIG. 10.

(Color online) (a) Temperature profile plot, and (b) temperature contour plot of a simulated device undergoing the 2nd Reset Pulse. The pulsing condition used was 10 ns 6 V. The temperature profile plot was extracted at nodes with the peak temperature in the NGST (circle) and GST (square) layers respectively.

Image of FIG. 11.
FIG. 11.

(Color online) (a) Temperature profile plot and (b) temperature contour plot of a simulated device undergoing the Set Pulse. The pulsing condition used was 400 ns 1.5 V. The temperature profile plot was extracted at nodes with the peak temperature in the NGST (circle) and GST (square) layers, respectively.

Image of FIG. 12.
FIG. 12.

(Color online) Plot of the thermal conductivity (k) and the electrical resistivity (r) of the phase change materials (NGST and GST) and barrier layer (Ta2O5) used in this work. The higher thermal conductivity of GST with respect to Ta2O5, coupled with the difference in electrical resistivities of both NGST and GST, contribute to the formation of the intermediate state.

Image of FIG. 13.
FIG. 13.

(Color online) Schematic showing the transition from one state to another. State I has the lowest resistance while State II the highest resistance. The Set and Reset pulses switch the device to the respective states independent of the previous state of the multi-level device.

Tables

Generic image for table
Table I.

The crystallization temperature TC and the melting temperature TM of the phase change materials nitrogen-doped GST (NGST) with 3.5 % nitrogen and undoped GST used in this work.

Loading

Article metrics loading...

/content/aip/journal/jap/110/12/10.1063/1.3672448
2011-12-29
2014-04-23
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer
http://aip.metastore.ingenta.com/content/aip/journal/jap/110/12/10.1063/1.3672448
10.1063/1.3672448
SEARCH_EXPAND_ITEM