(Color online) Schematic process flow of the proposed metal thin film memory in capacitive structure: (a) Piranha clean and BOE dip, (b) 5 nm thermal oxide growth by rapid thermal oxidation (RTO), (c) 15 nm Cr deposition by e-beam evaporation, (d) High K dielectric deposition by atomic layer deposition (ALD), (e) metal gate deposition by e-beam evaporation, and (f) device isolation by Cl2 etch and making back contact to lower substrate resistance.
Cross sectional HRTEM images of the fabricated memory device. (a) Low magnification TEM image shows Cr thickness of 17 (±0.5) nm and 30 nm Al2O3. (b) High resolution TEM image shows 5 (±0.5) nm tunnel oxide thickness and no apparent crystalline phases in Cr.
X ray diffraction patterns of (a) as deposited Cr thin film and (b) annealed Cr thin film on single crystal (100) Si substrate with 5 nm SiO2. XRD patterns show no evidence of Cr crystalline peak.
X-ray photoelectron spectroscopy (XPS) of Cr thin film deposited by e-beam evaporation. (a) Cr 2p spectrum and (b) O 1s spectrum indicate the existence of Cr2O3 as well as Cr near the surface
(Color online) (a) Capacitance-voltage (C-V) curve of the proposed memory device showing memory function with an ultra-wide memory window of 10 V at ± 18 V voltage sweep. (b) C-V curve of the control sample without metal thin film showing no hysteresis with steep transitions. (c) Memory device showing low leakage current density.
Band structure of our Cr/SiO2 junction and experimental data for retention time with a tunnel oxide of 5 nm. Measurements indicate a charge loss of 13% after 10 years, more than adequate for practical devices.
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