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Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions
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10.1063/1.3672411
/content/aip/journal/jap/111/7/10.1063/1.3672411
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/7/10.1063/1.3672411
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) MTJ device: (a) cross-sectional view, (b) R-I characteristic, (c) symbol.

Image of FIG. 2.
FIG. 2.

(Color online) Block diagram of the proposed 6-input LUT circuit.

Image of FIG. 3.
FIG. 3.

(Color online) Write operation: (a) circuit diagram, (b) measured waveform.

Image of FIG. 4.
FIG. 4.

(Color online) Performance comparisons between nonvolatile SRAM-based and proposed devices.

Image of FIG. 5.
FIG. 5.

(Color online) Monte-Carlo simulation results: (a) with no series/parallel connection of MTJ devices, (b) proposed.

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/content/aip/journal/jap/111/7/10.1063/1.3672411
2012-02-24
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/7/10.1063/1.3672411
10.1063/1.3672411
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