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Delayed mechanical failure of the under-bump interconnects by bump shearing
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10.1063/1.3702875
/content/aip/journal/jap/111/8/10.1063/1.3702875
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/8/10.1063/1.3702875
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Cross sectional scanning electron micrograph (SEM) of the copper pillar bump. The inset shows a schematic illustration of the SBST on the copper pillar.

Image of FIG. 2.
FIG. 2.

(a) Instantaneous and delayed failure behavior of under-bump interconnect, (b) cross sectional imaging of the fracture path after the catastrophic failure.

Image of FIG. 3.
FIG. 3.

The distribution of the instantaneous failure loads in a Weibull plot.

Image of FIG. 4.
FIG. 4.

(a) Dependence of on the holding load and temperature for chips with intact seal. The scattered marks are experimental data (in seconds), and the dash curves are model predictions. (b) Delayed failure is accelerated for chip with moisture seal broken followed by exposure to liquid water.

Image of FIG. 5.
FIG. 5.

Schematic curve of crack velocity (in semi-log scale) vs. energy release rate for silicon-based dielectrics susceptible to stress-corrosion.

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/content/aip/journal/jap/111/8/10.1063/1.3702875
2012-04-16
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Delayed mechanical failure of the under-bump interconnects by bump shearing
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/8/10.1063/1.3702875
10.1063/1.3702875
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