Cross sectional scanning electron micrograph (SEM) of the copper pillar bump. The inset shows a schematic illustration of the SBST on the copper pillar.
(a) Instantaneous and delayed failure behavior of under-bump interconnect, (b) cross sectional imaging of the fracture path after the catastrophic failure.
The distribution of the instantaneous failure loads in a Weibull plot.
(a) Dependence of on the holding load and temperature for chips with intact seal. The scattered marks are experimental data (in seconds), and the dash curves are model predictions. (b) Delayed failure is accelerated for chip with moisture seal broken followed by exposure to liquid water.
Schematic curve of crack velocity (in semi-log scale) vs. energy release rate for silicon-based dielectrics susceptible to stress-corrosion.
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