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A low-voltage high-speed electronic switch based on piezoelectric transduction
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10.1063/1.4704391
/content/aip/journal/jap/111/8/10.1063/1.4704391
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/8/10.1063/1.4704391

Figures

Image of FIG. 1.
FIG. 1.

(Left): PET with three terminals (gate, common, and sense), a PE element between the common and gate terminals and a PR element between the common and sense terminals. The constraining mechanical yoke is omitted for clarity, (center): Resistivity-pressure characteristic for a PR, SmSe, 16 (right): Symbols for noninverting (top) and inverting (bottom) PET.

Image of FIG. 2.
FIG. 2.

(Left): Physical structure of PET, showing PE, PR, and HYM, (right): Result of stress simulation showing high pressure in PR, lower pressure in PE, and negative pressure in HYM. The computations were performed using ANSYS software.

Image of FIG. 3.
FIG. 3.

Plot of vs. for a range of gate voltages from Eq. (8) , using parameters from Table I .

Image of FIG. 4.
FIG. 4.

Complementary 2-PET Circuits. (Left): 2-PET inverter and (right): 2-PET flip-flop.

Image of FIG. 5.
FIG. 5.

Plot of output voltage vs. input voltage for 2-PET inverter, parameters as Table I and Table II . V.

Image of FIG. 6.
FIG. 6.

Plot for determining output voltage v of complementary 2-PET flip-flop. Horizontal axis, v. vertical axis, black curve, Eq. (21) , red curve, v. V.

Image of FIG. 7.
FIG. 7.

PE and Piezoresistor (PR) with drive voltage and source impedance . and are the displacements of the PE and PR media, respectively.

Image of FIG. 8.
FIG. 8.

Single PET simulation. Top panel, plot of input voltage (red) and PR resistance (blue—note log scale) vs. time. Input voltage was . Middle panel, stress in PE (bottom) and PR (top) versus position (vertical) and time (horizontal). Lower panel, displacement in PE and PR, otherwise as middle panel. Assumes A/a = 9, , , and other parameters as in Table IV . The dimensionless input resistance, PE capacitance, and RC time are all 1, as is the sonic time (source resistance thus relatively high, ).

Image of FIG. 9.
FIG. 9.

Sketch of 3-PET ring oscillator. The dotted line represents the feedback loop. Line voltage is .

Image of FIG. 10.
FIG. 10.

Simulation of a 9-stage ring oscillator, showing PR resistance (top panel), interface displacement (middle panel), and output voltage (lower panel) vs. time. Color/line type code for each of the 9 inverters is, sequentially around the ring: blue, green, yellow, red, black, dashed blue, dashed green, dashed yellow, and dashed red. Relative units are on the left and physical units on the right. Parameters as Table IV . Line voltage is and . System initially equilibrated with feedback loop off, then at t = 10, the equilibrium is disturbed to start the oscillation.

Image of FIG. 11.
FIG. 11.

Switching frequency of a 9-stage inverter chain plotted as a function of line voltage for various cases: A/a = 9, and 25, and , 1, and 2. All cases except top curve in (a) have . The physical units on the top and right-hand axes in (a) assume l = 2 nm, (an estimated lower limit to avoid quantum tunneling). In (b), the PR area is , which may define the lithographic spacing. Line colors represent individual simulations. Solid lines have clean switching, dashed lines have incoherent switching because of too low voltage, and dotted lines have freeze-up because is enough to turn both PETs in the inverter completely on. Sonic time-based frequencies are shown as horizontal arrows in the left margins. is ; lower increases the frequency, but with the corresponding lower damping, can lead to undesirable oscillations.

Image of FIG. 12.
FIG. 12.

Switching characteristic of flip-flop. Top panel: PR resistance (full curve inverting PET, dashed curve noninverting PET), middle panel: interface displacement (curves as top panel), lower panel: R/W voltage (full curve), vs. time, dashed curve minus R/W voltage. Parameters as in Table IV . Line voltage is

Image of FIG. 13.
FIG. 13.

Plot of inverse LT of Eq. (B29) , with , with parameters , , , and .

Image of FIG. 14.
FIG. 14.

Inverter circuit with fixed input impedances R in each PET gate line.

Image of FIG. 15.
FIG. 15.

Plot of and inverter output given by Eqs. (B45) and (B49) , respectively. (black curve) given for (red curve), and (blue curve). a step function turned on at t = 0 ( ), with parameters , , , and .

Image of FIG. 16.
FIG. 16.

Green: V (volt); Red: per stage ( s), vs. L (nm). Parameters as Table I . , c = 4000 ms−1, and .

Tables

Generic image for table
Table I.

Typical PET parameter set.

Generic image for table
Table II.

PET device characteristics.

Generic image for table
Table III.

Normalizing factors.

Generic image for table
Table IV.

Simulation parameters.

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/content/aip/journal/jap/111/8/10.1063/1.4704391
2012-04-24
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: A low-voltage high-speed electronic switch based on piezoelectric transduction
http://aip.metastore.ingenta.com/content/aip/journal/jap/111/8/10.1063/1.4704391
10.1063/1.4704391
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