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Investigation of deep-level defects in conductive polymer on n-type 4H- and 6H-silicon carbide substrates using I-V and deep level transient spectroscopy techniques
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10.1063/1.4733569
/content/aip/journal/jap/112/1/10.1063/1.4733569
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/1/10.1063/1.4733569

Figures

Image of FIG. 1.
FIG. 1.

Schematic diagram of the Au/SPAN/SiC/Ni heterojunction.

Image of FIG. 2.
FIG. 2.

Semi-logarithmic plots of dark I–V characteristics of SPAN/4H-SiC heterojunctions in the temperature range of 20–440 K at 40 K intervals. The inset shows the corresponding linear plot at room temperature.

Image of FIG. 3.
FIG. 3.

Semi-logarithmic plots of dark I–V characteristics of SPAN/6H-SiC heterojunctions in the temperature range of 40–440 K at 40 K intervals. The inset shows the corresponding linear plots at room temperature.

Image of FIG. 4.
FIG. 4.

ln I 0/T 2 vs. 1000/T for the SPAN/SiC heterojunction.

Image of FIG. 5.
FIG. 5.

Temperature dependence of the experimental barrier height (φBo ) and ideality factor (n) determined from I–V characteristics of SPAN/4H-SiC and SPAN/6H-SiC heterojunctions in the temperature range of 20–440 K at 20 K intervals. The inset shows nkT vs. kT for SPAN/6H-SiC heterojunction.

Image of FIG. 6.
FIG. 6.

Temperature dependence of the experimental series resistance (Rs ) obtained from I–V in the temperature range of 20–440 K at 20 K intervals.

Image of FIG. 7.
FIG. 7.

The experimental C–V curves for SPAN/4H-SiC and SPAN/6H-SiC heterojunctions at 1 MHz and at room temperature. The inset shows the reverse bias region in more detail in a (1/C)2 -V plot. For reverse bias, a linear fit was obtained. The intercepts with the x axis are also shown as represented by the dashed line in the inset.

Image of FIG. 8.
FIG. 8.

The energy distribution profile of interface trap density obtained from the forward bias I–V characteristics of Au/SPAN/SiC/Ni heterojunctions.

Image of FIG. 9.
FIG. 9.

Comparison of conventional DLTS signal for SPAN/4H-SiC and SPAN/6H-SiC for the following conditions: VR  = −1 V, Vp  = 0 V, rate window = 500 s−1, and tP  = 1 ms. The inset shows Laplace DLTS data for SPAN/4H-SiC device at T = 266 K.

Image of FIG. 10.
FIG. 10.

Arrhenius plot for electron traps in SPAN/4H-SiC and SPAN/6H-SiC heterojunctions.

Image of FIG. 11.
FIG. 11.

Arrhenius plot for holes traps in SPAN/4H-SiC and SPAN/6H-SiC heterojunctions. The inset shows Laplace DLTS peaks amplitudes of the trap H14H and H24H, in SPAN/4H-SiC heterojunction, and H16H in SPAN/6H-SiC heterojunction as functions of the filling-pulse time.

Tables

Generic image for table
Table I.

Electron traps in SPAN/4H-SiC and SPAN/6H-SiC devices obtained by DLTS technique.

Generic image for table
Table II.

Hole traps in SPAN/4H-SiC and SPAN/6H-SiC devices obtained by DLTS technique.

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/content/aip/journal/jap/112/1/10.1063/1.4733569
2012-07-03
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Investigation of deep-level defects in conductive polymer on n-type 4H- and 6H-silicon carbide substrates using I-V and deep level transient spectroscopy techniques
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/1/10.1063/1.4733569
10.1063/1.4733569
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