1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Two-bit multi-level phase change random access memory with a triple phase change material stack structure
Rent:
Rent this article for
USD
10.1063/1.4765742
/content/aip/journal/jap/112/10/10.1063/1.4765742
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/10/10.1063/1.4765742

Figures

Image of FIG. 1.
FIG. 1.

Process flow for fabrication of PCRAM device having a triple PCM structure. (a) Bottom electrode (200 nm of TiW) formation. (b) Active area definition after deposition of 100 nm of SiO2 dielectric. (c) Triple PCM stack formation by sequential deposition of 22 nm of GST, 1 nm of SiN, 22 nm of NGST, 1 nm of SiN, 22 nm of AIST, and 10 nm of TiW. (d) 100 nm of dielectric deposition. (e) Top metallization (200 nm of TiW).

Image of FIG. 2.
FIG. 2.

Resistance-time plot showing the four states in a two-bit multi-level PCRAM device. The onset of the Reset and Set pulses are indicated by the vertical arrows. The resistance states (I, II, III, and IV) are also annotated in the graph.

Image of FIG. 3.
FIG. 3.

Retention plots of the same two-bit multi-level device as in Fig. 2 . The measurement was performed at room temperature. The pulse conditions used to switch the device to a particular state are also annotated in the graph. The device shows good retention for all four states.

Image of FIG. 4.
FIG. 4.

U-curve of a two-bit multi-level PCRAM device. The set and reset operations are indicated on the graph. The measurements were performed with a constant pulse width of 800 ns, and the pulse magnitude is shown on the horizontal scale. The device was reset back to the highest resistance level (state IV) before each measurement or data point was taken. The four multi-level states (states I, II, III, and IV) are stable and distinct.

Image of FIG. 5.
FIG. 5.

Box plots illustrating the distribution of resistance values for each state for a set of 10 measured devices. The devices show tight distributions of resistance values for each state.

Image of FIG. 6.
FIG. 6.

Endurance cycles of a two-bit multi-level device (indicated by the data points). The dashed lines illustrate the extrapolated endurance of the device to 107 cycles. The device shows good potential for high endurance. The resistance states are very stable, and the resistance windows are consistently large.

Image of FIG. 7.
FIG. 7.

(a) Simulated temperature versus time profiles of a two-bit multi-level device undergoing the state II reset pulse (20 ns and 3 V). The voltage pulse was applied from 0 to 20 ns. The temperature in AIST (plotted as square symbols), NGST (plotted as triangle symbols), and GST (plotted as circle symbols) were taken at points 1, 2, and 3, respectively, as indicated in (b). (b) Simulated temperature contour plot of the two-bit multi-level device undergoing the same state II reset pulse, taken at 20 ns after application of the pulse. The temperature versus time profiles, in (a), were extracted from the nodes labelled 1, 2, and 3.

Image of FIG. 8.
FIG. 8.

(a) Simulated temperature versus time profiles of a two-bit multi-level device undergoing the state III reset pulse (20 ns and 4.5 V). The voltage pulse was applied from 0 to 20 ns. The temperature in AIST (plotted as square symbols), NGST (plotted as triangle symbols), and GST (plotted as circle symbols) were taken at points 1, 2, and 3, respectively, as indicated in (b). (b) Simulated temperature contour plot of the two-bit multi-level device undergoing the same state III reset pulse, taken at 20 ns after application of the pulse. The temperature versus time profiles, in (a), were extracted from the nodes labelled 1, 2, and 3.

Image of FIG. 9.
FIG. 9.

(a) Simulated temperature versus time profiles of a two-bit multi-level device undergoing the State IV reset pulse (20 ns and 6 V). The voltage pulse was applied from 0 to 20 ns. The temperature in AIST (plotted as square symbols), NGST (plotted as triangle symbols), and GST (plotted as circle symbols) were taken at points 1, 2, and 3, respectively, as indicated in (b). (b) Simulated temperature contour plot of the two-bit multi-level device undergoing the same state IV reset pulse, taken at 20 ns after application of the pulse. The temperature versus time profiles, in (a), were extracted from the nodes labelled 1, 2, and 3.

Image of FIG. 10.
FIG. 10.

Simulated temperature versus time profiles of a two-bit multi-level device undergoing the state I set pulse (400 ns and 2 V). The temperature profiles were extracted from nodes roughly in the middle of the GST (circle symbols), NGST (triangle symbols), and AIST (square symbols) layers.

Image of FIG. 11.
FIG. 11.

Simulated temperature versus time profiles of a two-bit multi-level device undergoing the (a) state III set pulse (400 ns and 1 V), and (b) state II set pulse (400 ns and 1.5 V). The temperature profiles were extracted from nodes roughly in the middle of the GST (circle symbols), NGST (triangle symbols), and AIST (square symbols) layers.

Image of FIG. 12.
FIG. 12.

Schematic of the phase changing process of the three PCMs in a triple PCM mulit-level device (using the amorphization method). The state II reset pulse switches the device to state II, the state III reset pulse switches the device to state III, the state IV reset pulse switches the device to state IV, and the state I set pulse crystallizes the device back to state I. The device can switch to a particular state from any arbitrary state using the respective set or reset pulse.

Tables

Generic image for table
Table I.

The thermal conductivities (κ) and electrical resistivities (ρ) of as-deposited amorphous PCMs and SiN used in this work. Melting temperatures (TM ) and crystallization temperatures (TC ) of the PCMs are also listed.

Loading

Article metrics loading...

/content/aip/journal/jap/112/10/10.1063/1.4765742
2012-11-21
2014-04-24
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Two-bit multi-level phase change random access memory with a triple phase change material stack structure
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/10/10.1063/1.4765742
10.1063/1.4765742
SEARCH_EXPAND_ITEM