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Degradation of potential barriers in ZnO-based chip varistors due to electrostatic discharge
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10.1063/1.4742987
/content/aip/journal/jap/112/3/10.1063/1.4742987
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/3/10.1063/1.4742987

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic illustrations of fabricated ZnO chip varistors with 1.2-mm2 and 0.24-mm2 electrodes, and (b) waveforms of 30-kV ESD pulse (red line) used for ESD tests and actually applied ESD (black line) to the dummy integrated circuit with 50 Ω resistance protected by Pr-ZnO chip varistor with 1.2-mm2 electrode. Inset of (b) represents the schematic electrical circuit protected by the ZnO varistor.

Image of FIG. 2.
FIG. 2.

Schematic illustration of apparatus used for SSPM measurements under dc bias (top), and schematically illustrated potential and resistance profiles of ZnO-based varistor (bottom) obtained from SSPM images.

Image of FIG. 3.
FIG. 3.

I-V characteristics of (a) Pr-ZnO and (b) Bi-ZnO varistors with 1.2-mm2 electrode before (solid line) and after (dashed line) the application of 10 shots of 30-kV ESD pulses from each external electrode. Inset in (a) shows the direction of the applied ESD pulses. The I-V characteristics of (c) Pr-ZnO (0.24-mm2 electrode) and (d) Bi-ZnO varistors (1.2-mm2 electrode) with polished mirror surfaces for SSPM measurements before and after 10 applications of 30-kV ESD from one side. Inset of (c) shows the direction of the applied ESD pulses and the forward direction defined for I-V and SSPM measurements. The s secondary x- and y-axes represent the normalized voltage (V/mm) and current (A/mm2) estimated using the thickness of the ceramics and the electrode size.

Image of FIG. 4.
FIG. 4.

SSPM images and line profiles of surface potential and resistance under ±4 V after degradation for Pr-ZnO varistor with 0.24-mm2 electrode. In the SSPM images in (a) and (b), the contrast corresponds to the applied dc voltage and its distribution, and the axes represent the SSPM image positions. (c) The line profiles of the surface potential (black) and resistance (red) that correspond to the dashed lines in (a) and (b). Triangles indicate grain boundaries and electrode interfaces.

Image of FIG. 5.
FIG. 5.

SSPM images and line profiles of surface potential and resistance under ±8 V after degradation for Pr-ZnO varistor with 0.24-mm2 electrode. In SSPM images (a) and (b), the contrast corresponds to the applied dc voltage and its distribution, and the axes represent the position for SSPM images. (c) The line profiles of the surface potential (black) and resistance (red) that correspond to the dashed lines in (a) and (b). Triangles indicate grain boundaries andelectrode interfaces. White dashed circles in (a) and (b) and the arrows in (c) denote grain boundary degradation due to ESD application.

Image of FIG. 6.
FIG. 6.

SSPM images before (a-b) and after (c-d) degradation for Bi-ZnO varistors with 1.2-mm2 electrode. The forward and reverse directions are the same as those defined in I-V measurements, as shown in Figs. 3(c) and 3(d). The contrast corresponds to the applied dc voltage and its distribution, and the axes represent the SSPM image positions. The white dashed circles indicate the area degraded due to ESD application, which includes grain boundaries and electrode interfaces.

Image of FIG. 7.
FIG. 7.

Surface potential (black) and resistance (red) profiles before and after degradation of Bi-ZnO varistors with 1.2-mm2 electrode. These profiles were obtained by crossing the degraded area indicated by white circles in Fig. 6. Triangles indicate grain boundaries and electrode interfaces. The arrows in (a) show the degraded DSB and the Schottky barrier.

Image of FIG. 8.
FIG. 8.

C-t properties of (a) Pr-ZnO and (b) Bi-ZnO varistors with 1.2-mm2 electrode measured by changing dc pulse duration from 100 ns to 100 s. (c) The C-t properties of Pr-ZnO and Bi-ZnO varistors with 1.2-mm2 electrode after application of 5-kV ESD pulse. The dashed lines show capacitance before application of dc pulse and ESD.

Image of FIG. 9.
FIG. 9.

C-t properties (black) and ICTS spectra S(t) (red) measured at 32 °C of (a) Pr-ZnO and (b) Bi-ZnO varistors with 1.2-mm2 electrode. The duration of the applied dc pulse was set to 1 s. The dashed lines show capacitance before the application of dc pulse. (c) The temperature dependence of ICTS spectra S(t) for Bi-ZnO varistors measured at various temperatures from 32 to 70 °C. (d) Arrhenius plot of the time constant (τT2) for electron emission from the interfacial states.

Image of FIG. 10.
FIG. 10.

(a) C-t properties (line) and ICTS spectra S(t) (symbol) of Bi-ZnO varistor with 1.2-mm2 electrode before (black) and after degradation (red). (b) The ln(1/C-1/C0) versus time (t) plots of Pr-ZnO and Bi-ZnO varistors with 1.2-mm2 electrode. The slope in (b) is inversely proportion to the relaxation time (τ).

Tables

Generic image for table
Table I.

Characteristics of fabricated chip varistors.

Generic image for table
Table II.

Evaluated activation energies of interfacial states in ZnO varistors.

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/content/aip/journal/jap/112/3/10.1063/1.4742987
2012-08-03
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Degradation of potential barriers in ZnO-based chip varistors due to electrostatic discharge
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/3/10.1063/1.4742987
10.1063/1.4742987
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