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Physical aspects of low power synapses based on phase change memory devices
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Image of FIG. 1.
FIG. 1.

Illustration of biological synapse and the equivalent PCM synapse in a neural circuit connecting a spiking pre- and post-neuron.

Image of FIG. 2.
FIG. 2.

(a) I–V characteristics for PCM devices with 100 nm thick GST and GeTe layer starting from initially amorphous phase. (b) R-I characteristics of GST and GeTe PCM devices, with inset showing the PCM phase of intermediate resistance states. (c) R-V curves for GST devices with six different pulse widths. Read pulse = 0.1 V, 1 ms. The legend shows pulse widths.

Image of FIG. 3.
FIG. 3.

(a) Experimental LTP characteristics of GST PCM devices. For each curve, first a reset pulse (7 V, 100 ns) is applied followed by 30 consecutive identical potentiating pulses (2 V). Dotted lines correspond to the behavioral model fit described in Eqs. (3a) and (3b). (b) Experimental LTP characteristics of GeTe PCM devices. (c) Circuit-compatible (Sec. IV B) based LTP simulations for GST devices. (d) Circuit-compatible (Sec. IV B) simulations of the conductance evolution as a function of the applied voltage for GST devices with six different pulse widths. The legends in Figs. 3(a)–3(d) indicate pulse widths.

Image of FIG. 4.
FIG. 4.

Experimental LTD characteristics of GST and GeTe PCM devices. Inset shows simulated phase morphology of GST layer after the application of consecutive depressing pulses.

Image of FIG. 5.
FIG. 5.

(a) 2D Axi-symmetrical half cell description used for physical simulations. (b) Simulated time evolution of applied voltage pulse and drop across the device for a potentiating pulse. (c) Simulated maximum temperature in GST layer with the applied pulse. (d) Simulated current passing through the device during the applied pulse. (e) Simulated resistance of the device with the applied pulse.

Image of FIG. 6.
FIG. 6.

(a) Simulated depressing (reset) pulse indicating the instance of time snapshot. (b) Time snapshot of the simulated phase morphology of the GST phase change layer.

Image of FIG. 7.
FIG. 7.

(a) Simulated LTP curves while fixing the nucleation rate (NR) and varying the growth rate GR compared to GST (taken as reference: GR = 1, NR = 1). Corresponding simulations of GST layer morphology are shown (0th pulse: reset; 1st-5th: potentiating). (b) Simulated LTP curves while fixing the growth rate (GR = 1) and varying the nucleation rate (NR) compared to GST (taken as reference material: NR = 1, GR = 1). Corresponding simulation of GST layer morphology are also shown.

Image of FIG. 8.
FIG. 8.

Circuit schematic for the 2-PCM Synapse. The input of the current from the LTD devices is inverted in the post-synaptic neuron.

Image of FIG. 9.
FIG. 9.

Simulated two-layer fully connected feed, forward SNN with 70 fully connected neurons and about 2 million synapses.22

Image of FIG. 10.
FIG. 10.

Grey squares show video recorded data of cars passing on a freeway in AER format. Black squares show the sensitivity map of the neurons in the 1st layer of the neural network for both GST and GeTe. Each neuron becomes sensitive to a specific orientation of cars in a specific lane.

Image of FIG. 11.
FIG. 11.

Scaling trend of RESET and SET current for different PCM technologies (values extracted from the literature).


Generic image for table
Table I.

Fitting parameters of the behavioral model for 300 ns GST LTP curve and 100 ns GeTe LTP curve shown in Figs. 3(a) and 3(b), respectively.

Generic image for table
Table II.

Parameters used for the GST compact model simulations shown in Fig. 3(c).

Generic image for table
Table III.

Average car detection rate for the 6 lanes for GST and GeTe PCM synapses.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Physical aspects of low power synapses based on phase change memory devices