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Void evolution in silicon under inert and dry oxidizing ambient annealing and the role of a Si1−xGex epilayer cap
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10.1063/1.4751267
/content/aip/journal/jap/112/5/10.1063/1.4751267
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/5/10.1063/1.4751267

Figures

Image of FIG. 1.
FIG. 1.

Bright field XTEM images for furnace annealing done at 1080 °C for 30 min in N2 for (a) Si and (b) Si0.95Ge0.05/Si samples.

Image of FIG. 2.
FIG. 2.

Variation of (a) average void diameter and (b) average void density in Si and Si0.95Ge0.05/Si samples as a function of annealing temperature.

Image of FIG. 3.
FIG. 3.

Ge interdiffusion after annealing for 30 min at 1050 °C taking into account the damage created during 30 keV, 5 × 1016 cm−2 He+ implantation.

Image of FIG. 4.
FIG. 4.

Void size distribution for furnace annealing done at 1080 °C for 30 min in N2 for (a) Si and (b) Si0.95Ge0.05/Si samples.

Tables

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Table I.

Standard deviation (SD) of void size distribution.

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/content/aip/journal/jap/112/5/10.1063/1.4751267
2012-09-11
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Void evolution in silicon under inert and dry oxidizing ambient annealing and the role of a Si1−xGex epilayer cap
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/5/10.1063/1.4751267
10.1063/1.4751267
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