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Comparison of gate geometries for tunable, local barriers in InAs nanowires
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10.1063/1.4759248
/content/aip/journal/jap/112/8/10.1063/1.4759248
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/8/10.1063/1.4759248

Figures

Image of FIG. 1.
FIG. 1.

Top and bottom gated InAs nanowire devices. (a) SEM micrograph of top gated devices, TG1. Current flows through the InAs nanowire in response to a voltage applied between contact leads S and D. and denote contact gates used to modulate the interface resistance between nanowire and the contacts. Leads are the top gates (width 100 nm, pitch 250 nm) used to induce electrostatic barriers in the nanowire. Top left schematic shows a cross sectional view through one of the top gates. Top right schematic shows a cross sectional view along the axis of the nanowire. (b) SEM micrograph showing the bottom gated device, BG. Here, the gates inducing the electrostatic barriers, , are located below the nanowire (width 45 nm, pitch 75 nm) and there are no contact gates. Top schematics show the corresponding cross sectional views as in (a). For both types of devices, (a) and (b), the barrier gates are isolated from the nanowire by a oxide layer of thickness and 20 nm, respectively.

Image of FIG. 2.
FIG. 2.

Device conductance as a function of temperature and gate voltages. Roman numerals and dashed lines indicate regions with specific trends; regions with similar trends bear the same numeral. (a) Effect of the source contact gate, , on the conductance of the top gated device, TG1, as a function of temperature with and . (b) Effect of top gate, g5, on the conductance of device TG1 as a function of temperature with and . (c) Effect of bottom gate g2 on conductance of device BG as a function of temperature with .

Image of FIG. 3.
FIG. 3.

Extraction of gate induced barrier height above the electrochemical potential, , assuming thermally activated transport. (a) Left, logarithm of G/T vs 1/T for various for top gated device TG1. Solid lines are linear fits, the slope yielding the barrier height, . Right, same for bottom gate on the device BG, the different traces corresponding to the same gate voltages as on the left. (b) Left, extracted as a function of gate voltage, , for four top gates on the devices, TG1 and TG2. Solid lines are linear fits giving the electrostatic coupling of the gate to the wire. Right, same for three bottom gates on the device BG.

Image of FIG. 4.
FIG. 4.

Comparison of sweep-stability of top and bottom gates at . (a) Bias spectroscopy of top gated device TG1, showing Coulomb blockade regions in measured conductance when sweeping gate voltage and stepping bias voltage, . For the remaining gates, , and . Switches are marked by arrows, dashed line traces edge of Coulomb blockade region. (b) Bias spectroscopy of bottom gates device, BG, when sweeping the bottom gates and with the global back-gate and remaining gates grounded.

Tables

Generic image for table
Table I.

Device and gate characteristics for local top and bottom gates.

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/content/aip/journal/jap/112/8/10.1063/1.4759248
2012-10-23
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Comparison of gate geometries for tunable, local barriers in InAs nanowires
http://aip.metastore.ingenta.com/content/aip/journal/jap/112/8/10.1063/1.4759248
10.1063/1.4759248
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