(a) LTP block and (b) LTD block.
Schematic illustration of the designed electronic synapse.
(a) Vpre, (b) Vpost, (c) Vsp, (d) Vsd, (e) VLTP, (f) VLTD, and (g) Rm in time domain. LTP and LTD are realized with the designed synapse.
Width of LTP pulse (tw) as a function of the interval between pre- and post-spikes (td) at various Vbp.
(a) A three-neuron network constructed with the designed synapse; and (b) associative learning realized with the three-neuron network.
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