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Design of an electronic synapse with spike time dependent plasticity based on resistive memory device
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10.1063/1.4795280
/content/aip/journal/jap/113/11/10.1063/1.4795280
http://aip.metastore.ingenta.com/content/aip/journal/jap/113/11/10.1063/1.4795280
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) LTP block and (b) LTD block.

Image of FIG. 2.
FIG. 2.

Schematic illustration of the designed electronic synapse.

Image of FIG. 3.
FIG. 3.

(a) Vpre, (b) Vpost, (c) Vsp, (d) Vsd, (e) VLTP, (f) VLTD, and (g) Rm in time domain. LTP and LTD are realized with the designed synapse.

Image of FIG. 4.
FIG. 4.

Width of LTP pulse (tw) as a function of the interval between pre- and post-spikes (td) at various Vbp.

Image of FIG. 5.
FIG. 5.

(a) A three-neuron network constructed with the designed synapse; and (b) associative learning realized with the three-neuron network.

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/content/aip/journal/jap/113/11/10.1063/1.4795280
2013-03-15
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Design of an electronic synapse with spike time dependent plasticity based on resistive memory device
http://aip.metastore.ingenta.com/content/aip/journal/jap/113/11/10.1063/1.4795280
10.1063/1.4795280
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